• Journal of Power Electronics
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• v.15 no.4
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• pp.1085-1092
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• 2015

In this paper, the expressions of the estimated information of a single-phase enhanced phase-locked loop (EPLL), when input signal contains harmonics and a DC offset while the fundamental component takes step changes, are derived. The theoretical analysis results indicate that in the estimated information, the n^th-order harmonics cause n+1^th-order periodic ripples, and the DC offset causes a periodic ripple at the fundamental frequency. Step changes of the amplitude, phase angle and frequency of the fundamental component cause a transient periodic ripple at twice the frequency. These periodic ripples deteriorate the performance of the EPLL. A hybrid filter based EPLL (HF-EPLL) is proposed to eliminate these periodic ripples. A delay signal cancellation filter is set at the input of the EPLL to cancel the DC offset and even-order harmonics. A sliding Goertzel transform-based filter is introduced into the amplitude estimation loop and frequency estimation loop to eliminate the periodic ripples caused by the residual input odd-order harmonics and step change of the input fundamental component. The parameter design rules of the two filters are discussed in detail. Experimental waveforms of both the conventional EPLL and the proposed HF-EPLL are given and compared with each other to verify the theoretical analysis and advantages of the proposed HF-EPLL.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.104-106
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• 2018

The harmonics and the DC offset in the grid can cause serious synchronization problems for grid connected inverters (GCIs) which leads not able to satisfy the IEEE 519 and p1547 standards in terms of phase and frequency variations. In order to guarantee the smooth and reliable synchronization of GCIs with the grid, Phase Locked Loop (PLL) is the crucial element. Typically, the performance of the PLL is assessed to limit the grid disturbances e.g. grid harmonics, DC Offset and voltage sag etc. To ensure the quality of GCI, the PLL should be precise in estimating the grid amplitude, frequency and phase. Therefore, in this paper a novel Robust PLL technique called Digital Lock-in Amplifier (DLA) PLL is proposed. The proposed PLL estimate the frequency variations and phase errors accurately even in the highly distorted grid voltage conditions like grid voltage harmonics, DC offsets and grid voltage sag. To verify the performance of proposed method, it is compared with other six conventional used PLLs (CCF PLL, SOGI PLL, SOGI LPF PLL, APF PLL, dqDSC PLL, MAF PLL). The comparison is done by simulations on MATLAB Simulink. Finally, the experimental results are verified with Single Phase GCI Prototype.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.51 no.4
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• pp.175-182
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• 2002

This paper proposes an analytic method for measuring the accurate fundamental frequency component of a fault current signal distorted with a DC-offset, a characteristic frequency component, and harmonics. The proposed algorithm is composed of four stages: sine filer, linear filter, Prony's method, and measurement. The sine filter and the linear filter eliminate harmonics and the fundamental frequency component, respectively. Then Prony's method is used to estimate the parameters of the DC-offset and the characteristic frequency component. Finally, the fundamental frequency component is measured by compensating the sine-filtered signal with the estimated parameters. The performance evaluation of the proposed method is presented for a-phase to around faults on a 345 kV 200 km overhead transmission line. The EMTP is used to generate fault current signals under different fault locations and fault inception angles. It is shown that the analytic method accurately measures the fundamental frequency component regardless of the characteristic frequency component as well as the DC-offset.

• KIEE International Transactions on Power Engineering
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• v.5A no.2
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• pp.138-143
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• 2005

During faults, the voltage and current signals available to the relay are affected by the decaying dc component and harmonics. In order to make appropriate and accurate decisions, most of the relaying algorithms require the fundamental frequency phasor information that is immune to decaying dc effect and harmonics. The conventional Fourier ph as or estimation algorithm is affected by the presence of decaying-exponential transients in the fault signal. This paper presents a modified Fourier algorithm, which effectively eliminates the decaying dc component and the harmonics present in the fault signal. The decaying dc parameters are estimated by means of an out-of-band filtering technique. The decaying dc offset and harmonics are removed by means of a simple computational procedure that involves the design of two sets of Orthogonal digital OFT filters tuned at different frequencies and by creating three off-line look-up tables. The technique was tested for different decay rates of the decaying dc component. It was also compared with the conventional mimic plus the full cycle OFT algorithm. The results indicate that the proposed technique has a faster convergence to the desired value compared to the conventional mimic plus OFT algorithms over a wide range of decay rates. In all cases, the convergence to the desired value was achieved within one cycle of the power system frequency.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.393-394
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• 2020

In this paper, an improved rotor speed estimation in DFIG wind turbine systems based on a cascaded SOGI is proposed. Due to excellent harmonics and DC offset rejection capability of the cascaded SOGI, the accurate rotor speed estimation can be achieved despite the harmonics and sensing offset in DFIG currents. The simulation results have verified the validity of proposed method.

• ETRI Journal
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• v.27 no.5
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• pp.473-483
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• 2005

In this paper, we propose two LC voltage-controlled oscillators (VCOs) that improve both phase noise and tuning range. With both 1/f induced low-frequency noise and low-frequency thermal noise around DC or around harmonics suppressed significantly by the employment of a current-current negative feedback (CCNF) loop, the phase noise in the CCNF LC VCO has been improved by about 10 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise of the CCNF VCO was measured as -112 dBc/Hz at 6 MHz offset from 5.5 GHz carrier frequency. Also, we present a bandwidth-enhanced LC VCO whose tuning range has been increased about 250 % by connecting the varactor to the bases of the cross-coupled pair. The phase noise of the bandwidth-enhanced LC-tank VCO has been improved by about 6 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise reduction has been achieved because the DC-decoupling capacitor Cc prevents the output common-mode level from modulating the varactor bias point, and the signal power increases in the LC-tank resonator. The bandwidth-enhanced LC VCO represents a 12 % bandwidth and phase noise of -108 dBc/Hz at 6 MHz offset.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.5
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• pp.711-720
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• 1994

A distance relaying algorithm for detecting faults at power transmission line is presented in this paper. The algorithm is based on differential equation from relaton between voltage and current, which is composed of lumped resistance and inductance. During the fault transient state,the voltage and current signals are severely distorted due to the exponentially decaying DC offset and high frequency components, In spite of using small data, the presented integral method to evaluate R and L from voltage and current has high performance against these harmonics including DC offset. Therefore, the presented algorithm can be implemented with only a low order anti-aliasing analog filter and dosen't need any digital filter to remove specific components.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.138-145
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• 2015

In this paper, a novel static overmodulation scheme (OVM) for space-vector PWM (SVPWM) is proposed. The proposed static OVM scheme uses the concept of adding offset voltages in linear region as well as overmodulation region to fully utilize DC-link voltage. By employing zero sequence voltage injection, the proposed scheme reduces procedures for achieving SVPWM such as complicated gating time calculation. In addition, this paper proposes a stepwise discontinuous angle movement in high modulation region in order to reduce Total Harmonic Distortion (THD). The validity of the proposed scheme is verified through theoretical analysis and experimental results.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Journal of Power Electronics
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• v.16 no.1
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• pp.163-172
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• 2016

The modular multilevel converter (MMC) has been receiving increased attentions in recent years. The new modular multilevel converter is a derivative topology from the traditional MMC in which the number of sub-modules (SMs) necessitated by each phase can be reduced by one. This paper presents a phase-shifted carrier pulse-width modulation (PSC-PWM) for the new MMC with an optimal phase-shifted angle to suppress the harmonics of the output voltage. Further, the harmonic features when the capacitor voltage of the middle SM is selected as two different values are also investigated. Moreover, in order to avoid introducing an unnecessary dc offset current at the ac terminals of the new MMC, a novel capacitor voltage balancing scheme is proposed by adjusting the amplitude of the reference signals rather than the offset. Finally, the validity and effectiveness of the proposed modulation and balancing schemes have been verified by experimental results based on a three-phase prototype of the new MMC.