• 한국자기학회:학술대회 개요집
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• 한국자기학회 2017년도 임시총회 및 하계학술연구발표회
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• pp.159-159
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• 2017

• Journal of Advanced Marine Engineering and Technology
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• 제19권3호
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• pp.99-106
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• 1995

PWM(Pluse Width Modulation) induction motor drives are being used in greater numvers through a wide variety of industrial and commercial applications. In this paper, a new speed control algorithm (hybrid algorithm) for induction motor drives that uses regular sampled PWM and harmonic elimination PWM is presented. The hybrid algorithm in implemeted on the computer to obtain solutions from the calculation equations of the width of the pulses and the firing angles for the selected harmonic elimination. this paper describes the time delay effects and the suitable compensating methods moreover, optical transmission system for driving signals is proposed and is compared with general trnasmission system. The hybrid inverter was tested with induction motor, and these test results are shown that this hybrid inverter closely approximates and exhibits many of the desirable performance characteristic distortions and eliminated the objectionable harmonics. Finally, detailed experimental investigation of the proposed hybrid scheme in presented.

• Journal of Power Electronics
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• 제15권6호
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• pp.1619-1627
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• 2015

This paper presents a power system harmonic elimination using the mixed adaptive linear neural network and variable step-size leaky least mean square (ADALINE-VSSLLMS) control algorithm based active power filter (APF). The weight vector of ADALINE along with the variable step-size parameter and leakage coefficient of the VSSLLMS algorithm are automatically adjusted to eliminate harmonics from the distorted load current. For all iteration, the VSSLLMS algorithm selects a new rate of convergence for searching and runs the computations. The adopted shunt-hybrid APF (SHAPF) consists of an APF and a series of 7^th tuned passive filter connected to each phase. The performance of the proposed ADALINE-VSSLLMS control algorithm employed for SHAPF is analyzed through a simulation in a MATLAB/Simulink environment. Experimental results of a real-time prototype validate the efficacy of the proposed control algorithm.

• Journal of Power Electronics
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• 제18권6호
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• pp.1650-1658
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• 2018

Multilevel converters are being widely used in medium-voltage high-power applications including motor drive systems, utility power transmission, and distribution systems. Selective harmonic elimination (SHE) is a well-known modulation method to generate high quality output voltage waveforms. This paper presents a new simple practical method for generating a generalized five-level waveform without selected low order harmonics. This method is based on a phase-shifted expression for the SHE problem, which can analytically calculate the exact values of switching angles and the feasible modulation index range for three-level and five-level waveforms. The proposed method automatically determines the number of transitions between levels and generates proper output waveform without solving complex trigonometric equations. Due to the simplicity of the computational burden, the real-time implementation of the proposed algorithm can be performed by a simple processor. Simulation and experiment results verify the correctness and effectiveness of the proposed method.

• Journal of Power Electronics
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• 제16권4호
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• pp.1306-1315
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• 2016

Modern power systems driven by high-power converters have become inevitable in view of the ever increasing demand for electric power. The total power loss can be reduced by limiting the switching losses in such power converters; increased power efficiency can thus be achieved. A reduced switching frequency that is less than a few hundreds of hertz is applied to power converters that produce output waveforms with high distortion. Selective harmonic elimination pulse width modulation (SHEPWM) is an optimized low switching frequency pulse width modulation method that is based on offline estimation. This method can pre-program the harmonic profile of the output waveform over a range of modulation indices to eliminate low-order harmonics. In this paper, a SHEPWM scheme for three-phase three-leg neutral point clamped inverter is proposed. Aside from eliminating the selected harmonics, the DC capacitor voltages at the DC bus are also balanced because of the symmetrical pulse pattern over a quarter cycle of the period. The technique utilized in the estimation of switching angles involves the firefly algorithm (FA). Compared with other techniques, FA is more robust and entails less computation time. Simulation in the MATLAB/SIMULINK environment and experimental verification in the very large scale integration platform with Spartan 6A DSP are performed to prove the validity of the proposed technique.

• Journal of Power Electronics
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• 제16권2호
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• pp.512-521
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• 2016

Cascaded H-bridge multilevel (CHBML) inverters usually include a large number of isolated dc-voltage sources. Some faults in the dc-voltage sources result in unequal cell dc voltages. Unfortunately, the conventional phase-shifted carrier (PSC) PWM method that is widely used for CHBML inverters cannot eliminate low frequency sideband harmonics when the cell dc voltages are not equal. This paper analyzes the principle of sideband harmonic elimination, and proposes an improved PSCPWM that can eliminate low frequency sideband harmonics under the condition of unequal dc voltages. In order to calculate the carrier phases, it is necessary to solve transcendental equations for low frequency sideband harmonic elimination. Therefore, an approach based on the artificial bee colony (ABC) algorithm is presented in this paper. The proposed PSCPWM method enhances the reliability of CHBML inverters. The proposed PSCPWM is not limited to CHBML inverters. It can also be applied to other types of multilevel inverters. Simulation and experimental result obtained from a prototype CHBML inverter verify the theoretical analysis and the achievements made in this paper.

• 한국조명전기설비학회지:조명전기설비
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• 제2권2호
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• pp.64-70
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• 1988

교류 전동기의 가변속 구동에 있어서, 가변전압, 가변주파수 방식의 PWN 인버터가 널리 사용되고 있다. 본 연구에서는 3상 PWN 인버터의 출력 파형에 있어서 특정고조파제거를 위한 방법이 소개되며 그 타당성을 입증하기 위해 실험결과는 시뮬레이션 결과와 비교·검토된다. 제안된 PWN 방식은 유도 전동기뿐만 아니라 전압 조정기, UPS 등에도 사용 가능하다.

• 대한전기학회논문지:전력기술부문A
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• 제51권8호
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• pp.371-378
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• 2002

This paper presents the rapid and accurate algorithm for fault detection and location estimation in the transmission line. This algorithm uses wavelet transform for fault detection and harmonics elimination and utilizes least square error method for fault impedance estimation. Wavelet transform decomposes fault signals into high frequence component Dl and low frequence component A3. The former is used for fault phase detection and fault types classification and the latter is used for harmonics elimination. After fault detection, an adaptive data window technique using LSE estimates fault impedance. It can find a optimal data window length and estimate fault impedance rapidly, because it changes the length according to the fault disturbance. To prove the performance of the algorithm, the authors test relaying signals obtained from EMTP simulation. Test results show that the proposed algorithm estimates fault location within a half cycle after fault irrelevant to fault types and various fault conditions.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제48권12호
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• pp.691-700
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• 1999

This paper proposes a novel switching strategy of 1Mvar STATCON using cascade multilevel H-bridge inverter(HBI) for FACTS application. To control the reactive power instantaneously, the d-q dynamic system model is described and analyzed. A single pulse pattern based on the SHEM(Selective Harmonic Elimination Method) technique is determined from the look-up table to reduce the line current harmonics and a rotating fundamental frequency switching scheme is presented to adjust the DC voltage of each inverter capacitor at the same value. So the voltage unbalance problem between separately DC bus voltage is improved by using the proposed switching scheme. As a result, the presented inverter configuration not only reduces the system complexity by eliminating the isolation at the AC input side transformer but also improves the dynamic response to the step change of reactive power.

• 전기학회논문지P
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• 제64권2호
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• pp.79-84
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• 2015

Voltage sags are considered the dominant disturbances affecting power quality. Dynamic voltage restorers(DVRs) are mainly used to protect sensitive loads from the electrical network voltage disturbances such as sags or swells and could be used to reduce harmonic distortion of ac voltages. The typical DVR topology essentially contains a PWM inverter with LC Filter, an injection transformer connected between the ac voltage line and the sensitive load, and a DC energy storage device. For injecting series voltage, the PWM inverter is used and the passive filter consist of inductor(L) and capacitor(C) for harmonics elimination of the inverter. However there are voltage pulsation responses by the characteristic of the LC passive filter that eliminate the harmonics of the PWM output waveform of the inverter. Therefore, this paper presented design and feedback performance of LC filter used in the DVRs. The voltage control by LC filter should be connected in the line side since this feedback method allows a relatively faster dynamic response, enabling the elimination of voltage notches or spikes in the beginning and in the end of sags and strong load voltage THD reduction. Illustrative examples are also included.