• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.176-185
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• 1996

In this paper, we present the modified CMA (constant modulus algorithm) and LMS (least mean square) algorithms for digiCipher system with reduced hardware cost, in which the pipelined architecture is employed. They yield the performance comparable to that using floating-point operations. We show the effecstiveness of the proposed architecture through the implementation results using VHDL.

• Proceedings of the KIEE Conference
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• 1997.07c
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• pp.930-932
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• 1997

Logic Based Expert System (LBES) has the advantage of real-time inference. This paper shows a LBES for fault diagnosis of power system and proposes the hardware implementation of LBES. Besides, having a power system topology in memory chip, proposed system is apt to be applicable to other system with low changing cost.

• Honam Mathematical Journal
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• v.29 no.3
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• pp.415-425
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• 2007

The normal basis has the advantage that the result of squaring an element is simply the right cyclic shift of its coordinates in hardware implementation over finite fields. In particular, the optimal normal basis is the most efficient to hardware implementation over finite fields. In this paper, we propose an efficient parallel architecture which transforms the Gaussian normal basis multiplication in GF($2^m$) into the type-I optimal normal basis multiplication in GF($2^{mk}$), which is based on the palindromic representation of polynomials.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.8
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• pp.746-753
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• 2001

In this paper, we review the basic concept of Evolvable Hardware first. And we examine genetic algorithm processor and hardware reconfiguration method and implementation. By considering complexity and performance of hardware at the same time, we design genetic algorithm processor using modularization and parallel processing method. And we design frame that has connection structure and logic block on FPGA, and embody reconfigurable hardware that do so that this frame may be reconstructed by RAM. Also we implemented ECANS that information processing system such as living creatures'brain using this hardware reconfiguration method. And we apply ECANS which is implemented using the concept of Evolvable Hardware to time-series prediction problem in order to verify the effectiveness.

• Journal of IKEEE
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• v.22 no.1
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• pp.104-109
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• 2018

This paper presents a hardware design for the block encryption algorithm of ARIA which is used for standard in Korea. It presents a hardware-efficient design to increase the throughput for the ARIA algorithm using a high-speed pipeline architecture. We have used ROM for the S-box implementation. This approach aims to decrease the critical path delay of the encryption. In this paper, hardware was designed by VHDL, realized RTL level by Synplify which is synthesis tool and verified simulation by ModelSim. The ARIA algorithm is shown 68.3 MHz (Maximum operation frequency) to use Xilinx VertxE XCV Series device.

• ETRI Journal
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• v.34 no.1
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• pp.76-86
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• 2012

The block cipher ARIA has been threatened by side-channel analysis, and much research on countermeasures of this attack has also been produced. However, studies on countermeasures of ARIA are focused on software implementation, and there are no reports about hardware designs and their performance evaluation. Therefore, this article presents an advanced masking algorithm which is strong against second-order differential power analysis (SODPA) and implements a secure ARIA hardware. As there is no comparable report, the proposed masking algorithm used in our hardware module is evaluated using a comparison result of software implementations. Furthermore, we implement the proposed algorithm in three types of hardware architectures and compare them. The smallest module is 10,740 gates in size and consumes an average of 47.47 ${\mu}W$ in power consumption. Finally, we make ASIC chips with the proposed design, and then perform security verification. As a result, the proposed module is small, energy efficient, and secure against SODPA.

• Journal of IKEEE
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• v.24 no.2
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• pp.502-506
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• 2020

With the development of autonomous driving technology, the importance of object recognition technology is increasing. Haze removal is required because the hazy weather reduces visibility and detectability in object recognition. However, the image from which the haze has been removed cannot properly reflect the unique color, and a detection error occurs. In this paper, we use CIE1931 color coordinate system to extend or reduce the color area to provide algorithms and hardware that reflect the colors of the real world. In addition, we will implement hardware capable of real-time processing in a 4K environment as the image media develops. This hardware was written in Verilog and implemented on the SoC verification board.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.67 no.1
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• pp.9-14
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• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

• Journal of IKEEE
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• v.27 no.3
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• pp.296-302
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• 2023

As Multimedia industry has evolved, it has become possible to display resolutions in various formats. Therefore, the performance of a scaler algorithm that converts resolutions while maintaining high quality and its hardware implementation are important. Considering the hardware design of an image up/down scaler, this paper proposes a combinatorial scaler algorithm that uses modified bilinear interpolation in the vertical direction and bicubic interpolation in the horizontal direction to reduce the line memory burden. Through quantitative and qualitative evaluations, this paper compared the performance of the proposed algorithm with three other well-known algorithms, and also compared the hardware burden of its hardware implementation. This paper used a sinusoidal signal and eight typical images for performance evaluation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.799-808
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• 2007

BACnet is an international standard communication protocol especially designed for building automation and control systems. BACnet uses the Master-Slave/Token-Passing (MS/TP) protocol as one of its field-level networks. A BACnet MS/TP field controller prototype and MS/TP network monitoring system are developed in this study. This report introduces the design and implementation methodology of a BACnet MS/TP field controller hardware, firmware and protocol stack. This report also presents the implementation methodology of BACnet MS/TP network monitoring system using VTS (Visual Test Shell). The methodologies introduced in this report will facilitate the develop and implementation of the BACnet-based control systems in building automation area.