• Journal of KIISE:Software and Applications
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• v.34 no.8
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• pp.697-707
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• 2007

Since embedded software is very dependent for target hardware architecture, characteristics of the platform must be considered when designing the software. Furthermore, MPSoCs consists of heterogeneous hardware components that are specified in micro level. Thus mapping of embedded software for MPSoCs should be considered the characteristics. In this paper, we provide an approach to automatic mapping PIM (Platform Independent Model) of an embedded software to PSM(Platform Specific Model) for MPSoC(Multi Processor System On Chip) and verify its effectiveness with simulation. In the proposed approach, tasks are derived from an object oriented model based on the UML (Unified Modeling Language). And then the types of the derived tasks are identified. With the identified types and inter relationship between tasks, the tasks are assigned to appropriate heterogeneous hardware components. We expect that the approach improve accuracy of the assigning and concurrency of the deployed software.

• International Journal of Advanced Culture Technology
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• v.8 no.2
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• pp.1-5
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• 2020

As the world gradually advances to an aging society, the quality of human life is valued. Among them, 'quality of sleep' is very closely related to quality of life. Recently, Korea expanded health insurance coverage for "sleep disorders". Particularly, as the number of sleep multiple tests and prescriptions for sleep aids has increased rapidly, much attention has been focused on the related medical service environment. Therefore, this study looked at an in-depth interview of 11 hospitals to see what treatment delivery system is being established when the government applies health insurance for 'sleep disorders'. In conclusion, the organizations with the most average number of sleep polyp tests per day were found to have more sleep polyp labs (hardware) and more full-time specialists. Also, the polysomnography lab (hardware) and the specialist's full-time status (software) did not necessarily result in a "positive pressure regulator prescription" that can solve "sleep apnea" caused by "sleep ailments". Rather, it was found that the number of days of sleep multiple laboratories (hardware), the number of full-time specialists (software) or the specialty majors (software) had a greater impact. In particular, the higher the specialist's full-time personnel (software) index (=6.000), the higher the sleep-inducing agent prescription rate(=1.000), and the lower the specialist's full-time personnel (software) index (=1.000), the higher the sleep-inducer's prescription rate(= 0.010) Was low. In addition, even if the professional full-time personnel(software) index was the same (=1.000), the hospital type was lower as it was closer to the public hospital(=0.067) and higher at the specialized hospital (= 0.933). In the case of university hospitals, when the full-time specialists (software) are in the same condition (= 1.000), the frequency of use of the sleep laboratory (=1.000) and the sleep test rate (= 1.000) were all the same.

• International Journal of Naval Architecture and Ocean Engineering
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• v.1 no.2
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• pp.78-88
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• 2009

In shipbuilding industry, the manufacturing technology has advanced at an unprecedented pace for the last decade. As a result, many automatic systems for cutting, welding, etc. have been developed and employed in the manufacturing process and accordingly the productivity has been increased drastically. Despite such improvement in the manufacturing technology, however, development of an automatic system for fabricating a curved hull plate remains at the beginning stage since hardware and software for the automation of the curved hull fabrication process should be developed differently depending on the dimensions of plates, forming methods and manufacturing processes of each shipyard. To deal with this problem, it is necessary to create a "plug-in" framework, which can adopt various kinds of hardware and software to construct a full automatic fabrication system. In this paper, a framework for automatic fabrication of curved hull plates is proposed, which consists of four components and related software. In particular the software module for computing fabrication information is developed by using the ooCBD development methodology, which can interface with other hardware and software with minimum effort. Examples of the proposed framework applied to medium and large shipyards are presented.

• ETRI Journal
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• v.34 no.1
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• pp.76-86
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• 2012

The block cipher ARIA has been threatened by side-channel analysis, and much research on countermeasures of this attack has also been produced. However, studies on countermeasures of ARIA are focused on software implementation, and there are no reports about hardware designs and their performance evaluation. Therefore, this article presents an advanced masking algorithm which is strong against second-order differential power analysis (SODPA) and implements a secure ARIA hardware. As there is no comparable report, the proposed masking algorithm used in our hardware module is evaluated using a comparison result of software implementations. Furthermore, we implement the proposed algorithm in three types of hardware architectures and compare them. The smallest module is 10,740 gates in size and consumes an average of 47.47 ${\mu}W$ in power consumption. Finally, we make ASIC chips with the proposed design, and then perform security verification. As a result, the proposed module is small, energy efficient, and secure against SODPA.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.67 no.1
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• pp.9-14
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• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

• ETRI Journal
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• v.35 no.5
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• pp.931-934
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• 2013

The weight calculation in an iterative algorithm is the most computationally costly task in computed tomography image reconstruction. In this letter, a fast algorithm to speed up the weight calculation is proposed. The classic square pixel rotation approximate calculation method for computing the weights in the iterative algorithm is first analyzed and then improved by replacing the square pixel model with a circular pixel model and the square rotation approximation with a segmentation method of a circular area. Software simulation and hardware implementation results show that our proposed scheme can not only improve the definition of the reconstructed image but also accelerate the reconstruction.

• Journal of Computing Science and Engineering
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• v.3 no.3
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• pp.181-194
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• 2009

Flash memory is increasingly being used in a wide range of storage applications because of its low power consumption, low access latency, small form factor, and high shock resistance. However, the current platforms for flash memory software development do not meet the ever-increasing requirements of flash memory applications. This paper presents three different hardware platforms for flash memory/NVRAM (non-volatile RAM) software development that overcome the limitations of the current platforms. The three platforms target different types of host system and provide various features that facilitate the development and verification of flash memory/NVRAM software. In this paper, we also demonstrate the usefulness of the three platforms by implementing three different types of storage system (one for each platform) based on them.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.237-239
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• 2001

This paper describes the digital relay simulator system using digital signal processor. The simulator system has two parts, one is software and the other is hardware part. The simulation software has variety calculation engines ; EMTP simulation data file conversion, user define simulation data generation, sequence data generation, data analysis engines. etc, these are designed upon GUI. And simulator software provides easy control interface for users, the simulator software performs on every MS Windows OS. The simulator hardware design uses 32bit floating point DSP(TMS320C32) architecture to achieve flexibility and high speed operation.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.5 no.4
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• pp.18-25
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• 1996

In this study, we have developed the stereolithography system that supports the development of a products. This paper presents the development of the stereolithography system. The system is composed of hardware, software and control part. The software converts a STL file to NC data and displays the monitoring figure in control part. The hardware part deals with structure of machine. The most important theme in this paper is LG-SLCAM software. This software can generate NC data and scanning condition data from a STL file semiautimatically. On the basis of three diensional shapes, it makes data for support structure from STL file. The effectiveness of using out stereolithography system is confirmed by processes of good development.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.65-68
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• 2000

In this paper, as a compatible software radio transmission system, Digital-Radio conversion system which can directly change the digital signal generated by the logic circuit into radio signal is proposed. By the vector synthesis method, the digital signals can change directly into radio signal. If such a circuit is realized, RF circuit and an antenna can be composed by the simple one device, and the radio is directly controlled and performed by the software processing which is the essence of software radio. This Digital-Radio conversion system of this paper give many number of communication channels being offered by PN code and offer a hardware design flexibility by digitization, therefore it decrease the percentage ratio of hardware of system and give a more flexible function of software basis. In this paper, this proposed Digital-Radio conversion system is called D/R converter, and the principle of this D/R converter, radio signal generation algorithm is explained and the performance characteristics of proposed algorithm is shown in time base by the computer simulation method.