• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.3
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• pp.311-317
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• 2013

In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard for applying marine communications in order to multimedia transmission. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed partial memory structure in order to reduced the delay and high speed decoder is possible. The results of the simulation, when the max number of iteration set to 30 times, decoding throughput of HSS algorithm is 326 Mbit/s and decoding speed of proposed algorithm is 2.29 Gbit/s. So, decoding speed of proposed algorithm more than 7 times could be obtained compared to the HSS algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.9
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• pp.2029-2035
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• 2013

In this paper, we presented non-uniform quantization method for LDPC decoder specified in DVB-S2 standard. There are some problems in order to implement LDPC decoder in aspect to algorithm and implementation. In algorithm aspect, because of large number of iterations, LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. Therefore, this paper studies Horizontal Shuffle Scheduling (HSS) algorithm which reduced iteration number without performance loss. In aspect of implementation, there are some solutions to improve the decoding speed, however this paper focused on non-uniform quantization which reduce the quantization bits of LDPC decoder. In simulation results, Decoding throughput of HSS LDPC decoder based on non-uniform quantization is 816Mbps and it improved 12% compared to conventional one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.9
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• pp.2041-2047
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• 2013

In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed dc-split memory structure in order to reduced the delay and high speed decoder is possible. Finally, this paper presented maximum split memory and throughput for various coding rates in DVB-S2 standard.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1248-1255
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• 2012

LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies horizontal shuffle scheduling(HSS) algorithm and self-correction normalized min-sum(SC-NMS) algorithm. In the result, number of iteration is half than conventional algorithm and performance is almost same between sum-product(SP) and SC-NMS. Finally, This paper implements high-speed LDPC decoder based on FPGA. Decoding throughput is 816 Mbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.2
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• pp.140-145
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• 2013

This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mc${\rightarrow}$v message to 0 if there is an inconsistency between the signs of the current incoming messages Mv'${\rightarrow}$c and the sign of the previous incoming messages Moldv'${\rightarrow}$c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.

• Journal of Satellite, Information and Communications
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• v.6 no.2
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• pp.78-83
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• 2011

In this paper, we propose a computationally efficient early stopping method to reduce the average number of iterations. The conventional early stopping methods have too much computational complexity to compute the stopping criterion. Thus, only the hard decision based early stopping method is suitable to realize the hardware of LDPC decoder. However, this method also can increase the computational complexity of LDPC decoder. The proposed method can effectively reduce the computational complexity of stopping criterion as we do not compute hard decision, and we combine the stopping criterion with horizontal shuffling scheduling decoding scheme. The simulation results show that a new early stopping method achieves acceptable bit error rate performance also reduces the average number of iterations.

• Journal of the Korea Computer Industry Society
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• v.7 no.4
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• pp.437-446
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• 2006

Mobilecomputer offers more fundamental role than role assistance enemy of modern technology equipment and new Information <중략> These main weakness puts in structural relation between elements that compose system. Therefore, dynamics research that time urea of systematic adjustment has selected method code Tuesday nerve dynamics enemy who groping of approach that become analysis point is proper and do with recycling bioelectricity signal. Nature model of do living body signal digital analysis chapter as research result could be developed and scientific foundation groping could apply HSS (Hardware-software system) by rehalibitation purpose. Special quality that is done radish form Tuesday of bioelectricity signal formation furthermore studied, and by the result, fundamental process of bodysignal in do structure circuit form of analog - digital water supply height modelling do can.