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http://dx.doi.org/10.7840/kics.2013.38C.3.311

A Study on High Speed LDPC Decoder Algorithm Based on DVB-S2 Standard  

Jung, Ji Won (한국해양대학교 전파공학과)
Kwon, Hae Chan (한국해양대학교 전파공학과)
Kim, Yeong Ju (목포대학교 컴퓨터공학과)
Park, Sang Hyuk (목포대학교 정보통신공학과)
Lee, Seong Ro (목포대학교 정보전자공학과)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.38C, no.3, 2013 , pp. 311-317 More about this Journal
Abstract
In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard for applying marine communications in order to multimedia transmission. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed partial memory structure in order to reduced the delay and high speed decoder is possible. The results of the simulation, when the max number of iteration set to 30 times, decoding throughput of HSS algorithm is 326 Mbit/s and decoding speed of proposed algorithm is 2.29 Gbit/s. So, decoding speed of proposed algorithm more than 7 times could be obtained compared to the HSS algorithm.
Keywords
DVB-S2; Horizontal Shuffle Scheduling(HSS); Sj memory; edge memory; Check Node Update(CNU);
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