• 제목/요약/키워드: HEMT device

검색결과 112건 처리시간 0.027초

Metamorphic HEMT에서 low-k Benzocyclobutene (BCB)를 이용한 표면 passivation 비교 연구 (Comparative study of surface passivation for Metamorphic HEMT using low-k Benzocyclobutene(BCB))

  • 백용현;오정훈;한민;최석규;이복형;이성대;이진구
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.471-472
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    • 2006
  • The passivation technology is very important, because this technology can protect a device against the influence of ambient environment, and prevent the performance reduction. In this paper, we fabricated the $0.1{\mu}m\;{\Gamma}$-gate InAlAs/InGaAs metamorphic high electron mobility transistors (MHEMTs) on GaAs substrates using the low-k benzocyclobutene (BCB) and $Si_3N_4$ as a passivation and we performed the comparisons of characteristics of the MHEMTs. After passivation, the DC and RF measurement results were decreased either the conventional Si3N4 or BCB layers. The decrement of the BCB passivation was smaller than the $Si_3N_4$ passivation.

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중전력 주파수 3체배기 설계 및 제작 (Design and Fabrication of the Frequency Tripper for Medium Power)

  • 노희정;이병선
    • 전자공학회논문지 IE
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    • 제47권3호
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    • pp.47-52
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    • 2010
  • 본 논문에서 P-HEMT를 이용한 100 mW급 중전력 주파수체배기를 제안한다. 3차 고조파 성분을 발생 시키는 비선형 장치를 이용하여 2.4GHz의 입력을 3체배 하여 7.2GHz 주파수를 얻도록 설계하였다. 주파수 체배기는 로드풀 모의실험 방식을 이용하여 설게 하였고 기본파와 2차 고조파가 억압된 노치 필터를 사용 하였다. 15dBm 입력에 약21dBm의 출력을 얻도록 하였다 즉 6dB의 변환 이득을 얻었고 기본파에서 20dBc 2차 고조파에서 30dBc의 고조파 억압을 하였다.

InP 식각정지층을 갖는 InAlAs/InGaAs/GaAs MHEMT 소자의 항복 전압 개선에 관한 연구 (Simulation Study on the Breakdown Enhancement for InAlAs/InGaAs/GaAs MHEMTs with an InP-Etchstop Layer)

  • 손명식
    • 반도체디스플레이기술학회지
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    • 제12권3호
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    • pp.23-27
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    • 2013
  • This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess structures has been simulated and analyzed for the breakdown of the devices with the InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2V to almost 4V and that the saturation current at gate voltage of 0V is reduced from 90mA to 60mA at drain voltage of 2V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier layer and the $Si_3N_4$ passivation layer deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer. In the paper, the fully-recessed asymmetric gate-recess structure at the drain side shows the on-breakdown voltage enhancement from 2V to 4V in the MHEMTs.

역지향성 능동배열 안테나용 2-Port 주파수 혼합기의 설계 (Design of a 2-Port Frequency Mixer for the Retrodirective Active Array Antenna)

  • 전중창;김태수;김현덕
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2004년도 춘계종합학술대회
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    • pp.59-63
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    • 2004
  • 본 논문에서는 역지향성 능동배열 안테나용 2-포트 주파수 혼합기를 설계 제작하였다. 역지향성 안테나는 임의의 방향에서 입사하는 전파를 그 방향으로 되돌려 복사시키는 안테나 배열 시스템으로서, 주파수 혼합기는 반사파가 입사 반대방향의 파면(wave front)을 갖기 위한 공액변위기로 작용된다. 2-포트 주파수 혼합기에서는 RF/IF 신호가 동일 포트를 사용함으로써 입력단의 신호 결합회로를 사용하지 않아도 되는 장점을 갖는다. 비선형소자는 p-HEMT가 사용되었으며, -10㏈m의 LO 전력에서 변환손실 -l㏈와 RF 전력 -15㏈m의 1-㏈ 억압점이 측정되었다.

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Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

  • Byoung-Gue Min;Jong-Min Lee;Hyung Sup Yoon;Woo-Jin Chang;Jong-Yul Park;Dong Min Kang;Sung-Jae Chang;Hyun-Wook Jung
    • ETRI Journal
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    • 제45권1호
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    • pp.171-179
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    • 2023
  • We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13㎛-0.16㎛ to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.

Reverse Engineering을 이용한 $Al_{x}Ga_{1-x}As/In_{y}Ga_{1-y}$As P-HEMTs의 구조적 분석 (Structural analysis of $Al_{x}Ga_{1-x}As/In_{y}Ga_{1-y}$As P-HEMTs reverse engineering)

  • 김병헌;황광철;안형근;한득영
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.255-258
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    • 2001
  • In this paper, DC and small signal characteristics with different physical parameters are expected for p-HEMTs (Pseudomorphic High Electron Mobility Transistors) with different temperatures ranging from 300K to 623K which are widely used for a low noise and/or ultra high frequency device. A device of 0.2$\times$200 ${\mu}{\textrm}{m}$$^2$dimension having very low noise has been chosen to extract the experimental data. Theoretical prediction has been obtained using a simulaor(HELENA) which needs experimental input data extracted from reverse engineering process. From the results, relation between structural parameters and temperature dependency of electrical characteristics are qualitatively explained to use in the design of descrete and integrated circuits to guarantee the optimal operation of the system.

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고내압 전력 스위칭용 AlGaN/GaN-on-Si HEMT의 게이트 전계판 구조 최적화에 대한 이차원 시뮬레이션 연구 (Two-dimensional Simulation Study on Optimization of Gate Field Plate Structure for High Breakdown Voltage AlGaN/GaN-on-Si High Electron Mobility Transistors)

  • 이호중;조준형;차호영
    • 대한전자공학회논문지SD
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    • 제48권12호
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    • pp.8-14
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    • 2011
  • 본 논문에서는 이차원 소자 시뮬레이션을 활용하여 주어진 게이트-드레인 간격에서 AlGaN/GaN-on-Si HEMT (high electron mobility transistor) 의 고항복전압 구현을 위한 게이트 전계판의 최적화 구조를 제안하였다. 게이트 전계판 구조를 도입하여 게이트 모서리의 전계를 감소시켜 항복전압을 크게 증가시킬 수 있음을 확인 하였으며, 이때 전계판의 길이와 절연막의 두께에 따라 게이트 모서리와 전계판 끝단에서 전계분포의 변화를 분석하였다. 최적화를 위하여 시뮬레이션을 수행한 결과, 1 ${\mu}m$ 정도의 짧은 게이트 전계판으로도 효과적으로 게이트 모서리의 전계를 감소시킬 수 있으며 전계판의 길이가 너무 길어지면 전계판과 드레인 사이의 남은 길이가 일정 수준 이하로 감소되어 오히려 항복전압이 급격하게 감소함을 보였다. 전 계판의 길이가 1 ${\mu}m$ 일 때 최대 항복전압을 얻었으며, 게이트 전계판의 길이를 1 ${\mu}m$로 고정하고 $SiN_x$ 박막의 두께를 변화시켜본 결과 게이트 모서리와 전계판 끝단에서의 전계가 균형을 이루면서 항복전압을 최대로 할 수 있는 최적의 $SiN_x$ 박막 두께는 200~300 nm 인 것으로 나타났다.

Short Channel Analytical Model for High Electron Mobility Transistor to Obtain Higher Cut-Off Frequency Maintaining the Reliability of the Device

  • Gupta, Ritesh;Aggarwal, Sandeep Kumar;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제7권2호
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    • pp.120-131
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    • 2007
  • A comprehensive short channel analytical model has been proposed for High Electron Mobility Transistor (HEMT) to obtain higher cut-off frequency maintaining the reliability of the device. The model has been proposed to consider generalized doping variation in the directions perpendicular to and along the channel. The effect of field plates and different gate-insulator geometry (T-gate, etc) have been considered by dividing the area between gate and the high band gap semiconductor into different regions along the channel having different insulator and metal combinations of different thicknesses and work function with the possibility that metal is in direct contact with the high band gap semiconductor. The variation obtained by gate-insulator geometry and field plates in the field and channel potential can be produced by varying doping concentration, metal work-function and gate-stack structures along the channel. The results so obtained for normal device structure have been compared with previous proposed model and numerical method (finite difference method) to prove the validity of the model.

DC and RF Characteristics of $0.15{\mu}m$ Power Metamorphic HEMTs

  • Shim, Jae-Yeob;Yoon, Hyung-Sup;Kang, Dong-Min;Hong, Ju-Yeon;Lee, Kyung-Ho
    • ETRI Journal
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    • 제27권6호
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    • pp.685-690
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    • 2005
  • DC and RF characteristics of $0.15{\mu}m$ GaAs power metamorphic high electron mobility transistors (MHEMT) have been investigated. The $0.15{\mu}m{\times}100{\mu}m$ MHEMT device shows a drain saturation current of 480 mA/mm, an extrinsic transconductance of 830 mS/mm, and a threshold voltage of -0.65 V. Uniformities of the threshold voltage and the maximum extrinsic transconductance across a 4-inch wafer were 8.3% and 5.1%, respectively. The obtained cut-off frequency and maximum frequency of oscillation are 141 GHz and 243 GHz, respectively. The $8{\times}50{\mu}m$ MHEMT device shows 33.2% power-added efficiency, an 18.1 dB power gain, and a 28.2 mW output power. A very low minimum noise figure of 0.79 dB and an associated gain of 10.56 dB at 26 GHz are obtained for the power MHEMT with an indium content of 53% in the InGaAs channel. This excellent noise characteristic is attributed to the drastic reduction of gate resistance by the T-shaped gate with a wide head and improved device performance. This power MHEMT technology can be used toward 77 GHz band applications.

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Si MOSFET과 GaN FET Power System 성능 비교 평가 (Comparative Performance Evaluation of Si MOSFET and GaN FET Power System)

  • 안정훈;이병국;김종수
    • 전력전자학회논문지
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    • 제19권3호
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    • pp.283-289
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    • 2014
  • This paper carries out a series of analysis of power system using Gallium Nitride (GaN) FET which has wide band gap (WBG) characteristics comparing to conventional Si MOSFET-used power system. At first, for comparison of each semiconductor device, the switching-transient parameter is quantitatively extracted from released information of GaN FET. And GaN FET model which reflect this dynamic property is configured. By using this model, the performance of GaN FET is analyzed comparing to Si MOSFET. Also, in order to enable a representative assessment on the power system level, Si MOSFET and GaN FET are applied to the most common structure of power system, full-bridge, and each power systems are compared based on various criteria, such as performance, efficiency and power density. The entire process is verified with the aid of mathematical analysis and simulation.