• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.269-277
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• 2007

In this paper, we present a efficient transcoding method from MPEG-2 to H.264. The proposed transcoder is the transcoding method for spatial domain which consists of MPEG-2 decoder part and H.264 encoding part. In transcoder, we can get useful information to estimate less probable modes from MPEG-2 decoder. Using this information, H.264 encoder chooses the macroblock mode of I-frame and P-frame adaptively to reduce the whole complexity of the transcoder. Our experimental result shows that the proposed algorithm can archive about $30\sim60%$ computational saving without significant degradation of visual quality and increasing of bit rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.175-178
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• 2009

H.264/AVC is a video coding standard of ITU-T and ISO/IEC, and widely spreads its application due to its high compression ratio more than twice that of MPEG-2 and high image quality. In this paper, we explained Intra Prediction in H.264/AVC, which is able to achieve higher compressing efficiency from correlation removal of adjacent samples in spatial domain, and proposed efficient Intra Predictor architecture design for H.264/AVC decoder. The proposed system reduced computation cycle using processing element and precomputation processing element and also reduced the number of access to external memory using efficient register. We designed the proposed system with Verilog-HDL and verified with suitable test vector. The proposed Intra Predictor achieved about 60% cycle reduction comparing with existing Intra Predictors.

• The KIPS Transactions:PartD
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• v.14D no.7
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• pp.801-808
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• 2007

Video coding standards such as MPEG-2, MPEG-4, H.263, and H.264 transmit a compressed video data using wired/wireless communication line with limited bandwidth. Because highly compressed bit-streams is likely to fragile to error from channel noise, video is damaged by error. There have been many research works on error concealment techniques, which recover transmission errors at decoder side [1, 2]. We designed an error concealment technique for lost motion vectors of H.264 video coding. In this paper, we propose a Kalman filter based motion vector recovery scheme, and experimented with standard video sequences. The experimental results show that our scheme restores original motion vector with more precision of 0.91 - 1.12 on average over conventional H.264 decoding with no error recovery.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.71-76
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• 2008

H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.407-408
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• 2008

This paper presents a synchronous pipeline design for IP-based H.264 decoding system. The first optimization for pipelining aims at efficiently resolving the data dependency due to motion compensation/intra prediction feedback data flow in H.264 decoder. The second one would enhance the efficiency of execution per each pipelining stage to explore the optimized latency and stage number. Thus, the 3 stage pipeline of CAVLD&ITQ|MC/IP&Rec.|DF is obtained to yield the best throughput and implementation. In experiments, it is found that the synchronous pipelined H.264 decoding system, based on existing IPs, could deal with Full HD video at 125.34MHz, in real time.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.91-94
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• 2003

H.264/AVC is the upcoming video coding standard of ITU-T H.264 and ISO MPEG-4 AVC. The new standard can achieve a significant improvement up to 50％ in compression ratio compared to MPEG-4 advanced simple profile. In this paper, we propose the novel intra prediction scheme to speed up intra prediction process in H.264/AVC decoder and show the hardware architecture for it. The proposed scheme uses the concurrent processing of the 4$\times$4 intra prediction, which is based on that some 4$\times$4 block pairs in a 16$\times$16 luma block can be processed concurrently. The proposed scheme can reduce intra prediction time by 33 ％.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.47-52
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• 2009

H.264 video coding standard is widely used due to the high compression rate and quality. The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation and management of the reference pixels. The reference pixels read from external memory using efficient memory management for data reuse is necessary along with the high performance interpolators. We propose the architecture of a motion compensation unit for H.264 decoders. It is composed of 2-dimensional circular register files, a motion vector predictor and high performance interpolators with low complexity. The 2-dimensional circular register files reuse reference pixel data as much as possible, and feed reference pixel data to interpolators without any latency and complex logic circuits. We design a motion compensation unit and a intra-prediction unit and integrate them into a prediction unit and verify the operation and the performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.43-53
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• 2010

Wide deployment of high resolution video services leads to active studies on high speed video processing. Especially, prevalent employment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a multi-core platform. Parallel H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Multi-Threaded Parallelization(MTP). In MTP, to reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before the parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition(HD) and a full high-definition(FHD) video, respectively compared with that of popular existing method called 2Dwave.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.459-470
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• 2008

In this paper, we propose a fast ME (motion estimation) algorithm for MPEG-4 to H.264 Transcoder. Whereas 2 modes ($8{\times}8$, $16{\times}16$) are used for ME in MPEG-4 simple profile, ME using 7 modes is supported for further enhanced coding efficiency in H.264. The transcoding speed is affected dominantly by the computational complexity of encoder part in transcoder, where ME module of H.264 encoder has high complexity due to using 7 modes. In order to increase the speed of transcoding between MPEG-4 and H.264, we use 3 PMVs (predicted motion vectors) and the mode information of MBs (macroblocks) provided from the decoder part of transcoder. Since the proposed 3 PMVs are very close to an optimal motion vector, and we consider only some restricted modes according to the MB information transferred from decoder part, the proposed scheme can speed up the transcoding procedure without loss of image quality. We show experimental results which demonstrate the effectiveness of the proposed algorithm, where performance of our scheme is compared with that of the conventional fast algorithm for H.264.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.50-56
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• 2016

This paper proposes the architecture and design of intra prediction circuit for a multi-decoder supporting UHD images. The proposed circuit supports not only the latest video compression standard HEVC but also H.264. In addition to the basic function of performing intra prediction, this circuit has the capability of performing the reference sample filter operation defined in the H.264 standard, and the smoothing and strong sample filter operations defined in the HEVC standard. We reduced the circuit size by sharing the circuit blocks for common operations and internal storage, and improved the circuit performance by parallel processing. The proposed circuit was described at RTL using Verilog HDL and its functionality was verified by using NC-Verilog of Cadence. The RTL circuit was synthesized by using Design Compiler of Synopsys and 130nm standard cell library. The synthesized gate-level circuit consists of 69,694 gates and processes 100 ~ 280 frames per second for 4K-UHD HEVC images at the maximum operation frequency of 157MHz.