Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2008.06a
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- Pages.407-408
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- 2008
An optimization of synchronous pipeline design for IP-based H.264 decoder design
IP기반 H.264 디코더 설계를 위한 동기화 파이프라인 최적화
- Ko, Byung-Soo (Dept. of Computer Engineering Kwangwoon University) ;
- Kong, Jin-Hyeung (Dept. of Computer Engineering Kwangwoon University)
- Published : 2008.06.18
Abstract
This paper presents a synchronous pipeline design for IP-based H.264 decoding system. The first optimization for pipelining aims at efficiently resolving the data dependency due to motion compensation/intra prediction feedback data flow in H.264 decoder. The second one would enhance the efficiency of execution per each pipelining stage to explore the optimized latency and stage number. Thus, the 3 stage pipeline of CAVLD&ITQ|MC/IP&Rec.|DF is obtained to yield the best throughput and implementation. In experiments, it is found that the synchronous pipelined H.264 decoding system, based on existing IPs, could deal with Full HD video at 125.34MHz, in real time.
Keywords