• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.1349-1350
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• 2011

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1271-1274
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• 2006

Integrated a-Si:H gate driver with high reliability has been designed and simulated. The proposed a-S:H gate driver has only one reset transistor under AC driving for P and output node. These reset transistors show much less degradation than those under DC driving. The simulation results show that the lifetime and response time are improved significantly compared with those of the prior circuit.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.17-20
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• 2000

We have enhanced the yield of 0.25 ${\mu}{\textrm}{m}$ T-gate $Al_{0.25}$G $a_{0.75}$As/I $n_{0.2}$G $a_{0.8}$As P-HEMT using three-layer E-beam lithography process and selective etching process. The three-layer resist structure (PMMA/copolymer/ PMMA=2000 $\AA$/3000 $\AA$/2000 $\AA$) and three developers (Benzene：IPA=1：1,Methanol：IPA =1：1,MIBK：IPA=1：3) were used for fabrication of a wide-head T-gate by the conventional double E-beam exposure technology. Also 1 wt% citric acid： $H_2O$$_2$：N $H_{4}$OH(200m1：4ml：2.2ml) solution were used for uniform gate recess. The etching selectivity of GaAs over $Al_{0.25}$G $a_{0.75}$As is measured to be 80. So these P-HEMT processes can be used in X-band MMIC LNA fabrication.ion.ion.ion.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.883-886
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• 1999

We deposited tungsten gate electrode on gate SiO$_2$by thermal LPCVD with WF$_{6}$, SiH$_4$ and H$_2$. The resistivity was ~10$\mu$Ωcm and exhibited good adhesion ability on oxide when the temperature was higher than 40$0^{\circ}C$. We find that, however, both the low-field current and the charge-trapping characteristics were inferior to the control devices. The oxide degradation by fluorine during the tungsten deposition must be minimized to use the tungsten as alternative gate electrode.e.

• Transactions of Materials Processing
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• v.16 no.1 s.91
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• pp.3-8
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• 2007

Novel compression molding system for preform has been developed in this study. The preforms for injection blow molding and injection stretch blow molding are being manufactured by injection molding. However it contains gate mark that affects the bottom crack in the PET bottle. The compression molded preform does not contain gate mark, thus the appearance quality of bottle has been increased and the residual stress near gate(bottom of the bottle) has been reduced. The thickness distributions, haze, and transmittance are well accepted for the preform. Also, flow characteristics of the resin between a core and cavity could be analyzed through computer simulation.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.86-88
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• 2003

Gate 산화막을 high-k 물질인 $HfO_2$ 박막을 이용하여 N-type MOS field effect transistor를 제작하였다. 전극은 poly-Si 전극을 사용하였다. Gate 산화막은 ALD 로 $Hf(N(CH_3)_2)_4$ 원료를 이용하여 $HfO_2$ 박막을 형성하였다. 산화제는 $H_{2}O$ 와 $O_3$ 를 사용하였는데, $H_{2}O$ 가 약간 우수하였으나 그 차이는 크지 않았다. $HfO_2$ 를 증착하기 전에 in-situ 로 $O_3$ 를 흘려 줌으로써 $SiO_2$를 얇게 형성하였는데, 이 결과 threshold voltage 가 약 0.2V 높아지고 saturation current 가 커지는 것이 관찰되었다. 이러한 결과는 $HfO_2$ 박막을 직접 channel 위에 증착하는 것보다 $O_3$ 를 이용 얇은 $SiO_2$ 를 형성하고 그 위에 $HfO_2$ 박막을 증착하는 방법이 transistor의 특성을 향상시키는 데 도움이 된다.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.746-748
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• 1993

To overcome the problem of the diode reverse recovery in high switching frequency inverter, a new gate drive scheme is proposed for IGBT in this paper. Using this circuit, the reverse recovery current can be controlled and faster switching time can be achieved for hard switching inverter. The over-current protection method, which is suitable for the proposed gate driver, is also presented. The operation of the proposed circuit is investigated and its usefulness is verified through the experimental results.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.404-404
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• 2010

Despite much works have been done on the geometric structures of ripples, defects and edge atoms in a graphene device, there has been no report showing the direct correlation between the structures and the transport property. Unlike scanning tunneling microscopy or other electron microscopes, Scanning Gate Microscope (SGM) is a unique microscopic tool with which the local electronic structure and the transport property of a device can be measured simultaneously. We have performed a transport measurement in nanometer scale using a scanning gate microscope (SGM). We have found the nanoscopic pictures of electron and hole puddles and the role of graphene- device edges in the transport measurements. These experimental findings were successfully explained with a theoretical model.

• Korean Journal of Materials Research
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• v.28 no.4
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• pp.247-253
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• 2018

We examined the characteristics of indium tin zinc oxide (ITZO) thin film transistors (TFTs) on polyimide (PI) substrates for next-generation flexible display application. In this study, the ITZO TFT was fabricated and analyzed with a SiOx/SiNx gate insulator deposited using plasma enhanced chemical vapor deposition (PECVD) below $350^{\circ}C$. X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS) results revealed that the oxygen vacancies and impurities such as H, OH and $H_2O$ increased at ITZO/gate insulator interface. Our study suggests that the hydrogen related impurities existing in the PI and gate insulator were diffused into the channel during the fabrication process. We demonstrate that these impurities and oxygen vacancies in the ITZO channel/gate insulator may cause degradation of the electrical characteristics and bias stability. Therefore, in order to realize high performance oxide TFTs for flexible displays, it is necessary to develop a buffer layer (e.g., $Al_2O_3$) that can sufficiently prevent the diffusion of impurities into the channel.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.2061-2062
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• 2006

a-Si(amorphous silicon) TFT(thin film transistor)는 TFT-LCD(liquid crystal display)의 화소 스위칭(switching) 소자로 폭넓게 이용되고 있다. 현재는 a-Si을 이용하여 gate drive IC를 기판에 집적하는 ASG(amorphous silicon gate) 기술이 연구, 적용되고 있는데 이때 가장 큰 제약은 문턱 전압(Vth)의 이동이다. 특히 고온에서는 문턱 전압의(Vth) 이동이 가속화 되고, Ioff current가 증가 하게 되고, 저온($0^{\circ}C$)에서는 전류 구동능력이 상온($25^{\circ}C$) 상태에서 같은 게이트 전압(Vg)에 대해서 50% 수준으로 감소하게 된다. 특히 ASG 회로는 여러 개의 TFT로 구성되는데, 각각의 TFT가 고온에서 Vth shift 값이 다르게 되어 설계시 예상하지 못 한 고온에서의 화면 무너짐 현상 즉 고온 노이즈 불량이 발생 할 수 있다. 고온 노이즈 불량은 고온에서의 각 TFT의 문턱전압 및 $I_D-V_G$ 특성을 측정한 결과 고온 노이즈 불량에 영향을 주는 인자가 TFT의 width와 기생 capacitor비 hold TFT width가 영향을 주는 것으로 실험 및 시뮬레이션 결과 확인이 되었다. 발생 mechanism은 ASG 회로는 AC 구동을 하기 때문에 Voff 전위에 ripple이 발생 되는데 특히 고온에서 ripple이 크게 증가 하여 출력 signal에 영향을 주어 불량이 발생하는 것을 규명하였다.