• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.399-402
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• 2007

The effects of heat treatment on the electrical properties of strained-Si/SiGe-on-insulator (SGOI) devices were examined. We proposed the optimized heat treatment processes for improving the back interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA (rapid thermal annealing) before gate oxidation step and the post-RTA after source/drain dopant activation step, the electrical properties of strained-Si channel on $Si_{1-x}Ge_x$ layer were greatly improved, which resulting the improvement of the driving current, transconductance, and leakage current of SGOI-MOSFET.

• Proceedings of the Korean Vacuum Society Conference
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• 2008.02a
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• pp.305-305
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• 2008

• Journal of the Korean Physical Society
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• v.80
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• pp.1076-1080
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• 2022

For preventing a sneak current in the 3D cross-point array, the selection device is essentially necessary and an n-MOSFET has been used for the selection device. However, the three-terminal electrodes of n-MOSFET make to achieve a high density of a cross-point array difficult. As a solution, using a selector having two terminal electrodes has been intensively researched. We presented that the CuGeS₂/GeS₂-based super-linear-threshold-switching (SLTS) selector device with the insertion of optimal TiN liner thickness exhibited outstanding electrical characteristics and reliability. The dependency of electrical characteristics and reliability on various TiN liner thicknesses were investigated. In addition, the principles of reliability and electrical characteristics improvement were understood through the energy dispersive spectroscopy elemental mapping and line profile of Cu. The adequate amount of Cu distributed in GeS₂ resistive switching layer is a key factor to achieve excellent electrical characteristics and reliability for an ultra-high-density 3D cross-point array cell.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.17-18
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• 2008

In this paper, 1%-nitrogen doped Nickel was used for improvement of thermal stability of Ni-Germanide. Proposed Ni-N(1%)/TiN structure has shown better thermal stability, sheet resistance and less agglomeration characteristic than pure Ni/TiN structure. During the germanidation process, it is believed that the nitrogen atoms in the deposited nickel layer can suppress the agglomeration of Ni germanide by retarding the diffusion of Ni atoms toward silicon layer, hence improve the thermal stability of Ni-germanide.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.303-307
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• 2006

In this paper, we have designed the p-type metal-oxide semiconductor field-effect transistor(pMOSFET) for SiGe devices with gate lengths of $0.9{\mu}m$ and $0.1{\mu}m$using the TCAD simulators. The electrical characteristics of devices have been investigated over the temperatures of 300 and 77K. We have used the two carrier transfer models(hydrodynamic model and drift-diffusion model). We how that the drain current is higher in the hydrodynamic model than the drift-diffusion model. When the gate length is $0.9{\mu}m$, the threshold voltage shows -0.97V and -1.15V for 300K and 77K, respectively. The threshold voltage is, however, nearly same at $0.1{\mu}m$ for 300K and 77K.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.210-214
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• 2016

In this paper, the decrease in the contact resistance of Ni germanide/Ge contact was studied as a function of the thickness of the antimony (Sb) interlayer for high performance Ge MOSFETs. Sb layers with various thickness of 2, 5, 8 and 12 nm were deposited by RF-Magnetron sputter on n-type Ge on Si wafers, followed by in situ deposition of 15nm-thick Ni film. The contact resistance of samples with the Sb interlayer was lower than that of the reference sample without the Sb interlayer. We found that the Sb interlayer can lower the contact resistance of Ni germanide/Ge contact but the reduction of contact resistance becomes saturated as the Sb interlayer thickness increases. The proposed method is useful for high performance n-channel Ge MOSFETs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.99-100
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• 2009

SGOI 1T-DRAM cells with various Ge mole fractions were fabricated and compared to the SOI 1T-DRAM cell. SGOI 1T-DRAM cells have a higher leakage current than SOI 1T-DRAM cell at subthreshold region. The leakage current due to crystalline defects and interface states at Si/SiGe increased with Ge mole. This phenomenon causes sensing margin and the retention time of SGOI 1T-DRAMs decreased with increase of Ge mole fraction.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• ETRI Journal
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• v.28 no.2
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• pp.253-256
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• 2006

We propose a novel power metal oxide semiconductor field effect transistor (MOSFET) employing a strained-Si channel structure to improve the current drivability and on-resistance characteristic of the high-voltage MOSFET. A 20 nm thick strained-Si low field channel NMOSFET with a $0.75\;{\mu}m$ thick $Si_{0.8}Ge_{0.2}$ buffer layer improved the drive current by 20% with a 25% reduction in on-resistance compared with a conventional Si channel high-voltage NMOSFET, while suppressing the breakdown voltage and subthreshold slope characteristic degradation by 6% and 8%, respectively. Also, the strained-Si high-voltage NMOSFET improved the transconductance by 28% and 52% at the linear and saturation regimes.