• Proceedings of the KSME Conference
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• 2000.11a
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• pp.492-497
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• 2000

This paper focuses on the weight minimization of radial gate, as an extention of the previous work. Radial gates are commonly used to regulate the flow-rate of general purpose dams, due to its simplicity in manufacture and control. The present study identifies the optimum position of support point for 2 and 3 arm type radial gate, which guarantees the minimum weight satisfying strength constraint condition. These optimum designs are then compared with previously constructed radial gates. The results indicate that the weights of the optimized radial gates reduce by about 20%, compared to those of the conventionally designed radial gates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• Journal of the Optical Society of Korea
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• v.16 no.4
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• pp.432-442
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• 2012

In this paper, we propose, analyze and simulate the performances of some new plasmonic logic gates in two dimensional plasmonic waveguides with nanodisk resonators, using the numerical method of finite difference time domain (FDTD). These gates, including XOR, XNOR, NAND, and NOT, can provide the highly integrated optical logic circuits. Also, by cascading and combining these basic logic gates, any logic operation can be realized. These devices can be utilized significantly in optical processing and telecommunication devices.

• The Korean Journal of Nuclear Medicine
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• v.26 no.1
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• pp.95-100
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• 1992

The radioisotopic measurement of glomerular filtration rate (GFR) has required analysis of serial blood or urine samples over several hours, and does not allow measurement of separate renal function unless separate catherterization of individual ureters is done. Gates described isotopic method for the measurement of global and unilateral GFR based on the determination by scintillation camera of the fraction of the injected dose of $^{99m}Tc-diethylenetriaminepentaacetic$ acid (DTPA) present in the kidneys 2-3 minutes after its administration. We calculated GFR according to Gates' method in 58 adult patients with various levels of global renal function using $^{99m}Tc$ DTPA and validated this technique by correlation with 24 hour creatinine clearance. A good correlation was observed between 24 hour creatinine clearance and GFR calculated by Gates' formula, with an r value of 0.91 (p<0.01). We concluded that determination of GFR according to the Gates' formula allows good and reproducible prediction of GFR with great rapidity and simplicity rendering this technique suitable for clinical practice.

• Journal of the Architectural Institute of Korea Planning & Design
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• v.35 no.12
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• pp.115-125
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• 2019

Most of construction at urban area is now undertaking a redevelopment because currently the most of city is full. But the research about the collision of urban tissue at urban redevelopment area are very limited and there are many issues at urban redevelopment area. So the purpose of this study is to analyze the collision between different urban tissue at urban redevelopment area and suggest proper method for urban redevelopment. The area inside of four main gates, especially Chung Jin, Gong pyeong, Mu gyo- Da dong district are selected to analyze because the area inside of these gates is the oldest urban redevelopment area and each of them has a different redeveloped method. And current status of research area's urban tissue and collision situation are analyzed by macro and micro scale of view. The results of this study were as follows; Ignoring the timeline of the urban redevelopment process can be a major issue in collision between urban tissue. Therefore, the consideration of intermediate stage of redevelopment process is needed by making public area, a temporal use of vacant lot and changing architectural elements can make a harmony between different urban tissue.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1084-1087
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• 2000

This paper presents a new approach to evaluate the maximum number of simultaneous switching gates of a given combinational circuit. The new approach is based on an iterative method proposed by Sinogi et al. and applies a simulated annealing strategy to search jot a new solution. The experimental evaluation using ISCAS’85 benchmark circuits shows that the proposed approach has attained an excellent improvement compared with other rotated methods including the iterative method.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.32 no.4
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• pp.211-222
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• 2020

This study suggested a method calculating the influence of effluent discharge from Saemangeum sluice-gates using the particle tracking model. For 2017, we presented the seasonal effects of effluent discharge as probability spatial distributions and compared with the results of the water age, one of the indicators of transport time scale. The influence of sluice-gates effluent discharge increases radially around Sinshi or Gaseok gates, which are expected to be biased toward the south in winter and north in summer due to the effect of seasonal winds. Although the results of the prediction are limited to the 2017 situation, the method of calculating the influence of sluice-gates effluent discharge using the Lagrangian particle tracking model can be used to predict the future of the around Saemangeum.

• Structural Engineering and Mechanics
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• v.17 no.5
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• pp.611-626
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• 2004

On the basis of a structural analysis of radial gate (i.e. Tainter gate), the current paper focuses on weight minimization according to the location of the arms on a radial gate. In spite of its economical significance, there are hardly any previous studies on the optimum design of radial gate. Accordingly, the present study identifies the optimum position of the support point for a radial gate that guarantees the minimum weight satisfying the strength constraint conditions. This study also identifies the optimum position for 2 or 3 radial arms with a convex cylindrical skin plate relative to a given radius of the skin plate curvature, pivot point, water depth, ice pressure, etc. These optimum designs are then compared with previously constructed radial gates. Local genetic and hybrid-type genetic algorithms are used as the optimum tools to reduce the computing time and enhance the accuracy. The results indicate that the weights of the optimized radial gates are appreciably lower than those of previously constructed gates.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.17-25
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• 2008

The differential power attack (DPA)[8] is a very powerful side-channel attack tool against various cryptosystems and the masking method[10] is known to be one of its algorithmic countermeasures. But it is non-trivial to apply the masking method to non-linear functions, especially, to arithmetic adders. This paper proposes simple and efficient masking methods applicable to arithmetic adders. For this purpose, we use the fact that every combinational logic circuit (including the adders) can be decomposed into basic logic gates (AND, OR, NAND, NOR, XOR, XNOR, NOT) and try to devise efficient masking circuits for these basic gates. The resulting circuits are then applied to the arithmetic adders to get their masking algorithm. As applications, we applied the proposed masking methods to SEED and SHA-1 in hardware.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1538-1544
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• 2006

This paper proposes a non-systolic parallel $AB^2+C$ Computing unit based on irreducible AOP order m of $GF(2^m)$. Proposed circuit have only AND gates and EX-OR gates, composes of cyclic shift operation, multiplication operation power operation power-sum operation and addition operation using a merry irreducible AOP. Suggested operating a method have an advantage high speed data processing, low power and integration because of only needs AND gates and EX-OR gates. $AB^2+C$ computing unit has delay-time of $T_A+(1+[log^m_2])T_X$.