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A Base AOP Bit-Parallel Non-Systolic for $AB^2+C$ Computing Unit for $GF(2^m)$  

Hwang Woon-Taek (시립 인천전문대학)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.10, no.9, 2006 , pp. 1538-1544 More about this Journal
Abstract
This paper proposes a non-systolic parallel $AB^2+C$ Computing unit based on irreducible AOP order m of $GF(2^m)$. Proposed circuit have only AND gates and EX-OR gates, composes of cyclic shift operation, multiplication operation power operation power-sum operation and addition operation using a merry irreducible AOP. Suggested operating a method have an advantage high speed data processing, low power and integration because of only needs AND gates and EX-OR gates. $AB^2+C$ computing unit has delay-time of $T_A+(1+[log^m_2])T_X$.
Keywords
$AB^2+C$; Cyclic Shift Systolic; AOP; Power-sum;
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Times Cited By KSCI : 1  (Citation Analysis)
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