• 센서학회지
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• 제29권1호
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• ETRI Journal
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• 제39권5호
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• pp.737-745
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• 2017

A 6-GHz-to-18-GHz monolithic nonuniform distributed power amplifier has been designed using the load modulation of increased series gate capacitance. This amplifier was implemented using a $0.25-{\mu}m$ AlGaN/GaN HEMT process on a SiC substrate. With the proposed load modulation, we enhanced the amplifier's simulated performance by 4.8 dB in output power, and by 13.1% in power-added efficiency (PAE) at the upper limit of the bandwidth, compared with an amplifier with uniform gate coupling capacitors. Under the pulse-mode condition of a $100-{\mu}s$ pulse period and a 10% duty cycle, the fabricated power amplifier showed a saturated output power of 39.5 dBm (9 W) to 40.4 dBm (11 W) with an associated PAE of 17% to 22%, and input/output return losses of more than 10 dB within 6 GHz to 18 GHz.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제2권3호
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• pp.103-110
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• 2013

논리 노력[1, 2]의 기법은 회로의 지연 값을 간단한 필산으로 신속하게 측정할 수 있는 기술이다. 이 기법은 설계 공정 시간을 절약하는 장점도 있지만 고정 지연이라는 조건에서 논리 경로의 면적이나 전력 소비를 최소화하여 설계할 수 없는 단점이 있다. 이 단점을 보완하는 방법을 논문[3]에서 제안하였지만, 논리 경로가 하나인 회로에만 국한되어 적용할 수 있는 방법이었다. 본 논문에서는, 균형 지연 모델을 기초로, 다중 논리 경로의 회로에 적용할 수 있는 향상된 게이트 크기 결정 방법을 제한하고자 한다. 시뮬레이션 결과, 기존 논리노력 방법과 비교하면 전력 소비 측면에서 거의 같았지만 회로의 설계 공간 측면에서는 약 52%의 효율성을 보였다.

• Korea-Australia Rheology Journal
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• 제12권1호
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• pp.83-92
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• 2000

In resin transfer molding (RTM) process, preplaced fiber mat is set up in a mold and thermoset resin is injected into the mold. An important interest in RTM process is to minimize cycle time without sacrificing part quality or increasing cost. In this study, the numerical simulation and optimization process in filling stage were conducted in order to determine the optimum gate locations. Control volume finite element method (CVFEM) was used in this numerical analysis with the coordinate transformation method to analyze the complex 3-dimensional structure. Experiments were performed to monitor the flow front to validate simulation results. The results of numerical simulation predicted well the experimental results with every single, simultaneous and sequential injection procedure. We performed the optimization analysis for the sequential injection procedure to minimize fill time. The complex geometry of an automobile bumper core was chosen. Genetic algorithm was used in order to determine the optimum gate locations with regard to 3-step sequential injection case. These results could provide the information of the optimum gate locations in each injection step and could predict fill time and flow front.

• 실천공학교육논문지
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• 제9권2호
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• pp.119-124
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• 2017

사출성형 시 유압실린더의 힘으로 스크류가 앞으로 전진하는 동안, 금형의 러너시스템은 성형품 형상의 캐비티 내를 충진시키는 유로로 용융된 수지의 충진, 패킹과정에 관계되며, 이는 스프루(sprue), 러너(runner), 게이트(gate)에 의해서 성형품의 외관, 수지의 물성, 치수 정밀도 및 성형 사이클 등에 큰 영향을 준다. 러너, 게이트 설계가 잘못된 피드시스템은 다양한 성형불량을 일으키므로 이를 방지할 수 있는 최적의 러너밸런스를 유지하는 것이 중요하다. 사출금형을 제작하는 업체에서 응용할 수 있는 실무적인 금형기술 지식을 향상시키기 위해서 기술적인 애로분야에 대한 기술지도를 바탕으로 금형기술 과정의 훈련모델을 제시한다.

• 한국전기전자재료학회논문지
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• 제35권3호
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• pp.264-268
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• 2022

High pressure deuterium (HPD) annealing is an advancing technology for the fabrication of modern semiconductor devices. In this work, gate-enclosed FETs are fabricated on a silicon substrate as test vehicles. After a cycle for the HPD annealing, the device parameters such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), off-state current (I_OFF), and gate leakage (I_G) were measured and compared depending on the HPD. The HPD annealing can passivate the dangling bonds at Si-SiO₂ interfaces as well as eliminate the bulk trap in SiO₂. It can be concluded that adding the HPD annealing as a fabrication process is very effective in improving device reliability, performance, and variability.

• Transactions on Electrical and Electronic Materials
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• 제9권6호
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• pp.247-250
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• 2008

Hafnium dioxide ($HfO_2$) thin film as a gate dielectric for organic thin film transistors is prepared by plasma enhanced atomic layer deposition (PEALD). Mostly crystalline of $HfO_2$ film can be obtained with oxygen plasma and with water at relatively low temperature of $200^{\circ}C$. $HfO_2$ was deposited as a uniform rate of $1.2\;A^{\circ}$/cycle. The pentacene TFT was prepared by thermal evaporation method with hafnium dioxide as a gate dielectric. The electrical properties of the OTFT were characterized.

• 한국콘크리트학회:학술대회논문집
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• 한국콘크리트학회 2006년도 춘계학술발표회 논문집(I)
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• pp.350-353
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• 2006

We enhance the stability of SaeManGeum Drainage Sluice Gate Bridge. We prevent a destruction disaster of it. We extend the life cycle of it. So We have developed the safety control system to manage the facility of bridge to the continuance. In this study, sensitive sensor and measuring instrument has been taken to consider the characteristic of the box-girder type concrete bridge. And CDMA type has adapted for wireless communication. Control program has been developed on web base. In this program, the advanced systems have applied like this; the setup of control range for management from the statistical analysis, the evaluation system for force and deformation and the control system for a heavy vehicle permit.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1301-1304
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• 2008

In this study, we used a multiple phase scheme for the clock in the dual-pull-down driver for TFT display panels. In this scheme, the turn-on time for the transistors in the dual-pull-down structure was reduced from 1/2 to 1/4 or 1/8 of the period cycle time. While keeping proper operation of the transistor size of circuit was fine tuned to achieve an optimal performance. The relation between the active time and the transistor dimensions was obtained for the optimal design.

• 대한전자공학회논문지
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• 제26권5호
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• pp.145-151
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• 1989

본 논문에서는 semi-custom 방식의 레이아웃 설계중 게이트 배선 설계에서 배선의 효율을 높이기 위한 전처리 과정에 대해 논한다. Global 배선 설계의 결과로 주어진 각 채널에서의 핀 정보중 논리적으로 등가인 핀의 위치를 교환함으로써 detailed 배선에서 발생하는 싸이클을 해소할 수 있으며, 신호선의 분할에 의해 이웃하는 채널에서 중복으로 연결되는 신호선이 제거됨으로써 트랙수의 증가를 억제한다.