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http://dx.doi.org/10.3745/KTCCS.2013.2.3.103

Gate Sizing Of Multiple-paths Circuit  

Lee, Seungho (울산대학교 전기공학부)
Chang, Jongkwon (울산대학교 전기공학부)
Publication Information
KIPS Transactions on Computer and Communication Systems / v.2, no.3, 2013 , pp. 103-110 More about this Journal
Abstract
Logical Effort [1, 2] is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. The method of overcoming the shortcomings is shown in [3], but it is constrained for a single logical path. This paper presents an advanced gate sizing method in multiple logical paths based on the equal delay model. According to the results of the simulation, the power dissipation for both the existing logical effort method and proposed method is almost equal. However, compared with the existing logical effort method, it is about 52 (%) more efficient in space.
Keywords
Logical Effort; Optimizing Power-Delay; Equal Delay Model; Gate Sizing;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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