• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.111-114
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• 2008

We studied the influence of nanocrystalline silicon (nc-Si) thin film thickness on top gate nc-Si thin film transistor (TFT) fabricated at $180^{\circ}C$. The nc-Si thickness affects the characteristics of nc-Si TFT due to the nc-Si growth similar to a columnar. As the thickness of nc-Si increases from 40 nm to 200 nm, the grain size was increased from 20 nm to 40 nm. Having a large grain size, the thick nc-Si TFT surpasses the thin nc-Si TFT in terms of electrical characteristics such as field effect mobility. The channel resistance was decreased due to growth of the grain. We obtained the experimental results that the field effect mobility of the fabricated devices of which nc-Si thickness is 60, 90 and 130 nm are 26, 77 and $119\;cm^2/Vsec$, respectively. The leakage current, however, is increased from $7.2{\times}10^{-10}$ to $1.9{\times}10^{-8}\;A$ at $V_{GS}=-4.4\;V$ when the nc-Si thickness increases. It is originated from the decrease of the channel resistance.

• Korean Journal of Materials Research
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• v.15 no.5
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• pp.301-305
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• 2005

We fabricated nickel silicide layers on whole non-patterned wafers from $p-Si(100)SiO_2(200nm)$/poly-Si(70 nm)mn(40 nm) structure by 40 sec rapid thermal annealing of $500\~900^{\circ}C$. The sheet resistance, cross-sectional microstructure, surface roughness, and phase analysis were investigated by a four point probe, a field emission scanning electron microscope, a scanning probe microscope, and an X-ray diffractometer, respectively. Sheet resistance was as small as $7\Omega/sq$. even at the elevated temperature of $900^{\circ}C$. The silicide thickness and surface roughness increased as silicidation temperature increased. We confirmed the nickel silicides iron thin nickel/poly-silicon structures would be a mixture of NiSi and $NiSi_2$ even at the $NiSi_2$ stable temperature region.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.1-9
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• 2000

A new method, the external resistance method (ERM method), is proposed for accurate extraction of the gate bias-dependent effective channel carrier mobility (${\mu}_{eff}$) and separated parasitic source/drain resistances ($R_S$ and $R_D$) of n-channel MOSFET's. The proposed ERM method is applied to n-channel LDD MOSFETs with two different gate lengths ($W_m/L_m=30{\mu}m/0.6{\mu}m,\;30{\mu}m/1{\mu}m$) in the linear mode of current-voltage characteristics ($I_D-V_{GS},\;V_{DS}$). We also considered gate voltage dependence of separated $R_2$ and $R_D$ in the accurate modeling and extraction of effective channel carrier mobility. Good agreement of experimental data is observed in submicron n-channel LDD MOSFETs. Combining with capacitance-voltage characteristics, the ERM method is expected to be very useful for accurate and efficient extraction of ${\mu}_{eff},\;R_D,\;R_S$, and other characteristic parameters in both symmetric and asymmetric structure MOSFET's in which parasitic resistances are critical to the improvement of high speed performance and reliability.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.1
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• pp.13-15
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• 2004

The current driven in an MOSFET is limited by the intrinsic channel resistance. All the other parasitic elements in a device structure play a significant role and degrade the device performance. These other resistances need to be less than 15％ of the channel resistance. To achieve the requirements, we should investigate the methodology of separation and quantification of those resistances. In this paper, we developed the extraction method of resistances using calibrated TCAD simulation. The resistance of the extension region is also partially determined by the formation of a surface accumulation region that forms under the gate in the tail region of the extension profile. This resistance is strongly affected by the abruptness of the extension profile because the steeper the profile is, the shorter this accumulation region will be.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.21-25
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• 2008

In this study, to maximize RF performance of MOSFETs, $f_T$ and $f_{max}$ dependent data on $W_u$ are measured and newly analyzed by extracting small-signal model parameters. From the physical analysis results, it is found that a peak value of $f_T$ is generated by $W_u$-independent parasitic gate-bulk capacitance at narrow $W_u$ and the wide width effect of reducing the increasing rate of transconductance at wide $W_u$. In addition, it is revealed that a maximum value of $f_{max}$ is caused by the non-quasi-static effect that the gate resistance is greatly reduced at narrow $W_u$ and becomes constant at wide $W_u$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.82-90
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• 1995

We proposed SAW (Self-Algined Selectively Grown W-Gate) MOSFET structure, and strudied electrical characteristics of the fabricated SAW MOSFETs. The threshold volgate of 0.21${\mu}$m SAW NMOSFET was 0.18 V and that of 0.24 ${\mu}$m SAW PMOSFET was -0.16 V. The subthreshold slope was 74 mV/decade for NMOSFET and 82 mV/decade for PMOSFET. The maximum transconductance of NMOSFET and PMOSFET, at V$_{GS}$=2.5 V and V$_{DS}$=1.5 V, were260 mS/mm and 122 mS/mm. The measured saturation drain current at V$_{GS}$=V$_{DS}$ =2.5 V was 0.574 mA/${\mu}$m for NMOSFET and -0.228 mA/${\mu}$m for PMOSFET. The gate resistance of SAW MOSFET was about m$\Omega$cm and the n+-p junction capacitance of SAW MOSFET was about 10% lowas than that of the conventional MOSFET's.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.3
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• pp.146-153
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• 2006

We have been investigating InGaAs HEMTs as a future high-speed and low-power logic technology for beyond CMOS applications. In this work, we have experimentally studied the role of the side-recess spacing $(L_{side})$ on the logic performance of 50 nm $In_{0.7}Ga_{0.3}As$ As HEMTs. We have found that $L_{side}$ has a large influence on the electrostatic integrity (or short channel effects), gate leakage current, gate-drain capacitance, and source and drain resistance of the device. For our device design, an optimum value of $L_{side}$ of 150 nm is found. 50 nm $In_{0.7}Ga_{0.3}As$ HEMTs with this value of $L_{side}$ exhibit $I_{ON}/I_{OFF}$ ratios in excess of $10^4$, subthreshold slopes smaller than 90 mV/dec, and logic gate delays of about 1.3 ps at a $V_{CC}$ of 0.5 V. In spite of the fact that these devices are not optimized for logic, these values are comparable to state-of-the-art MOSFETs with similar gate lengths. Our work confirms that in the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs FETs hold considerable promise.

• Journal of Sensor Science and Technology
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• v.30 no.6
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• pp.436-440
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• 2021

The impact of the gate length (L_g) on the DC and high-frequency characteristics of indium-rich In_0.8Ga_0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (L_SD) of 0.8 ㎛ with different values of L_g ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (V_T) roll-off behavior against L_g was observed clearly, and the maximum transconductance (g_{m_max}) improved as L_g scaled down to 19 nm. In particular, the device with an L_g of 19 nm with an L_SD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a g_{m_max} of 2.5 mS/㎛, On resistance (R_ON) of 261 Ω·㎛, current-gain cutoff frequency (f_T) of 738 GHz, and maximum oscillation frequency (f_max) of 492 GHz. The results indicate that the reduction of L_g to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.626-632
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• 1995

In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 1997.10a
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• pp.11-13
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• 1997

Abstract - An electronic starter using MOSFET has been designed to take advantage of ideal preheating and starting features which can extend the lifetime of fluorescent lamps. The preheating circuit of the developed electronic starter is consisted of four parts - afull-wave rectifier circuit, an FET switching circuit a timer circuit for the gate switching, and a circuit for end-of-life protection. The circuit is analyzed by using PSpice simulation, and is improved to give an appropriate starting-time through control of R-C time constant of the timer circuit. And the circuit is also provided with an end-of-life protection feature, which utilizes the negative resistance characteristics of a thermistor that is thermally linked to FET through a heatsink. This also protects the FET from any overheating problems. From the results of simulation it is possible to obtain an appropriate value on the starting time for proper ignition and also it is verified that the limit for resistance of the thermistor is dependant on the value of resistance is the timer circuit