• Title/Summary/Keyword: Gate resistance

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Analysis of Effective Gate resistance characteristics in Nano-scale MOSFET for RFIC (RFIC를 위한 Nano-scale MOSFET의 Effective gate resistance 특성 분석)

  • 윤형선;임수;안정호;이희덕
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.11
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    • pp.1-6
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    • 2004
  • Effective gate resistance, extracted by direct extraction method, is analyzed among various gate length, in nanoscale MOSFET for RFIC. Extracted effective gate resistance is compared to measured data and verified with simplified model. Extracted parameters are accurate to 10GHz. In the same process technology effect has a different kind of gate voltage dependency and frequency dependency compared with general effective gate resistance. Particularly, the characteristic of effective gate resistance before and after threshold voltage is noticeable. When gate voltage is about threshold voltage, effective gate resistance is abnormally high. This characteristic will be an important reference for RF MOSFET modeling using direct extraction method.

Negative Resistance cCaracteristic in Gate Circuit of SCR (SCR의 Gate 회로에서의 부성저항특성)

  • Byung Chuel Bark
    • 전기의세계
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    • v.23 no.6
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    • pp.56-59
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    • 1974
  • It is well-known that the anode circuit of SCR has the current controlled negative resistance characteristic. Recently the present auther has shown that the gate circuit of SCR has the voltage controlled negative resistance characteristic for the constant anode voltage. It is shown of the equivalent model to SCR(when conducting) the voltage controlled negative resistance characteristic for gate circuit. And it is possible to make SCR gate oscillators with their desired characteristic for illustration.

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Design of Unified Trench Gate Power MOSFET for Low on Resistance and Chip Efficiency (낮은 온저항과 칩 효율화를 위한 Unified Trench Gate Power MOSFET의 설계에 관한 연구)

  • Kang, Ey-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.10
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    • pp.713-719
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    • 2013
  • Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have optimal designed planar and trench gate power MOSFET for high breakdown voltage and low on resistance. When we have designed $6,580{\mu}m{\times}5,680{\mu}m$ of chip size and 20 A current, on resistance of trench gate power MOSFET was low than planar gate power MOSFET. The on state voltage of trench gate power MOSFET was improved from 4.35 V to 3.7 V. At the same time, we have designed unified field limit ring for trench gate power MOFET. It is Junction Termination Edge type. As a result, we have obtained chip shrink effect and low on resistance because conventional field limit ring was convert to unify.

FinFET Gate Resistance Modeling and Optimization (FinFET 게이트 저항 압축 모델 개발 및 최적화)

  • Lee, SoonCheol;Kwon, Kee-Won;Kim, SoYoung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.8
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    • pp.30-37
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    • 2014
  • In this paper, the compact model for FinFET gate resistance is developed. Based on the FinFET geometry and material, the value of the gate resistance is extracted by Y-parameter analysis using 3D device simulator, Sentaurus. By dividing the gate resistance into horizontal and vertical components, the proposed gate resistance model captures the non-linear characteristics. The proposed compact model reflects the realistic gate structure which has two different materials (Tungsten, TiN) stacked. Using the proposed model, the number of fins for the minimum gate resistance can be proposed based on the variation of gate geometrical parameters. The proposed gate resistance model is implemented in BSIM-CMG. A ring-oscillator is designed, and its delay performance is compared with and without gate resistance.

Design and Analysis of 16 V N-TYPE MOSFET Transistor for the Output Resistance Improvement at Low Gate Bias (16 V 급 NMOSFET 소자의 낮은 게이트 전압 영역에서 출력저항 개선에 대한 연구)

  • Kim, Young-Mok;Lee, Han-Sin;Sung, Man-Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.21 no.2
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    • pp.104-110
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    • 2008
  • In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

Analysis of Transient Characteristics for IGBTs with Gate resistances (게이트저항에 따른 IGBT의 과도 특성 해석)

  • Ryu, Se-Hwan;Lee, Myung-Soo;Won, Chang-Sub;An, Hyung-Keun;Han, Deuk-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.173-174
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    • 2006
  • In this paper we proposed transient model for NPT(Non Punch-Through) IGBT(Insulated Gate Bipolar Transistor) with gate resistances. As gate resistance increases, turn-off time increases. But If gate resistance is small, overshoot voltage increase. To analyze the effect of gate resistance, the transient model is made and the experiments are conducted. We used gate resistances of values; 8[$\Omega$], 140[$\Omega$], 810[$\Omega$] for simulations and experiments. We compared theoretical and experimental results and obtained good agreements.

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Analysis of Electrical Characteristics of Shield Gate Power MOSFET for Low on Resistance (차폐형 게이트 구조를 갖는 전력 MOSFET의 전기적 특성 분석에 관한 연구)

  • Kang, Ey-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.30 no.2
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    • pp.63-66
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    • 2017
  • This research was about shielded trench gate power MOSFET for low voltage and high speed. We used T-CAD tool and carried out process and device simulation for exracting design and process parameters. The exracted parameters was used to design shieled and conventional trench gate power MOSFET. And The electrical characteristics of shieled and conventional trench gate power MOSFET were compared and analyzed for their power device applications. As a result of analyzing electrical characteristics, the recorded breakdown voltages of both devices were around 120 V. The electric distributions of shielded and conventional trench gate power MOSFET was different. But due to the low voltage level, the breakdown voltage was almost same. And the other hand, the threshold voltage characteristics of shielded trench gate power MOSFET was superior to convention trench gate power MOSFET. In terms of on resistance characteristics, we obtained optimal oxied thickness of $3{\mu}m$.

A SOI LDMOS with Trench Drain and Graded Gate (트렌치 드레인과 경사진 게이트를 갖는 SOI LDMOS)

  • Kim, Sun-Ho;Choi, Yearn-Ik
    • Proceedings of the KIEE Conference
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    • 2000.07c
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    • pp.1797-1799
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    • 2000
  • A SOI LDMOS with trench drain and graded gate is proposed to improve the on resistance. The proposed structure can decrease the on resistance by reducing the path of electron current. Simulation results by SUPREM and MEDICI have shown that the on resistance of the LDMOS with trench drain and graded gate was 14.8 % lower than conventional LDMOS with graded gate.

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Development of Low-Vgs N-LDMOS Structure with Double Gate Oxide for Improving Rsp

  • Jeong, Woo-Yang;Yi, Keun-Man
    • Transactions on Electrical and Electronic Materials
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    • v.10 no.6
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    • pp.193-195
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    • 2009
  • This paper aims to develop a low gate source voltage ($V_{gs}$) N-LDMOS element that is fully operational at a CMOS Logic Gate voltage (3.3 or 5 V) realized using the 0.35 μm BCDMOS process. The basic structure of the N-LDMOS element presented here has a Low $V_{gs}$ LDMOS structure to which the thickness of a logic gate oxide is applied. Additional modification has been carried out in order to obtain features of an improved breakdown voltage and a specific on resistance ($R_{sp}$). A N-LDMOS element can be developed with improved features of breakdown voltage and specific on resistance, which is an important criterion for power elements by means of using a proper structure and appropriate process modification. In this paper, the structure has been made to withstand the excessive electrical field on the drain side by applying the double gate oxide structure to the channel area, to improve the specific on resistance in addition to providing a sufficient breakdown voltage margin. It is shown that the resulting modified N-LDMOS structure with the feature of the specific on resistance is improved by 31%, and so it is expected that optimized power efficiencies and the size-effectiveness can be obtained.

The fabrication process and optimum design of RESURF EDMOSFETs for smart power IC applications (Smart power IC용 RESURF EDMOSFETs의 제조공정과 최적설계)

  • 정훈호;권오경
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.7
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    • pp.176-184
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    • 1996
  • To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${\Omega}{\cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${\Omega}{\cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.

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