• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.747-750
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• 2003

We have studied PHEMTs optimization by means of fabrication of PHEMTs. All PHEMTs have been fixed with a gate length of 0.1 ${\mu}{\textrm}{m}$, a gate head size of 0.75${\mu}{\textrm}{m}$, and two gate fingers. We have measured the characteristics of PHEMTs with variation of source-drain spacing, pad size, and gate width. As a result, we have found the enhanced characteristics of $I_{dss}$, $S_{21}$, $h_{21}$, $f_{T}$, $f_{max}$, and $G_{ms}$ with increasing gate width. Also, $g_{m}$ has improved with decreasing source-drain spacing, and $S_{21}$ has improved with deceasing pad size.e.e.e.e.

• 대한전자공학회논문지
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• 제26권5호
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• pp.117-126
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• 1989

본 논문에서는 게이트 어레이 방식의 레이아웃 설계를 위한 새로운 배치 알고리듬을 제안한다. 제안된 배치 알고리듬은 서로 크기가 다른 마크로셀을 처리할 수 있으며, I/Q pad의 위치를 고려함으로써 칩의 내부 영역과 I/Q pad간의 배선을 효율적으로 자동화한다. 알고리듬은 초기 분할, 초기 배치 개선의 3단계로 구성된다. 초기 분할 단계에서는 각 I/Q pad의 위치를 고려하여 clustering에 의해 전체 회로를 5그룹으로 분할한다. 초기 배치 단계에서는 각 I/Q pad 및 주변 그룹과의 연결도를 고려한 clustering/min-cut 분할에 의해 각 셀의 위치를 할당한다. 또한, 배치 개선에서는 확률적 배선 밀도 함수를 도입하여 칩내의 배선 밀도를 균일화하기 위한 셀 이동 알고리듬을 제안한다.

• 대한방사선기술학회지:방사선기술과학
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• 제42권3호
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• pp.175-180
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• 2019

In this study, we have researched the effectiveness of silicone pad. A distribution of scatter ray in mammography was evaluated using Monte-Carlo (MC) simulation technique and then a silicone pad was applied to remove the scatter ray for improving image quality. Molybdenum target and Molybdenum filter combination made a difference of 59.8% to a number of photon at 17.5 keV. On the other hand, Tungsten target and Rhodium filter showed a variation of 24.5% at 20 keV. Mean 68 of SNR was increased in Selenia and mean 1.04 of SNR was raised in Senographe. Silicone pad was significantly effective to reduce the scatter ray that was generated by primary X-ray. It can decrease an absorption rate of scatter ray to patient body and whilst it improve the image quality from increasing SNR.

• 한국전자통신학회논문지
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• 제9권8호
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• pp.853-859
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• 2014

본 연구에서는 핀치오프 된 cold-FET에서 게이트와 드레인 패드를 디임베딩하여 얻어지는 Z-파라미터와 게이트와 드레인 패드 커패시턴스를 제외한 핀치오프 된 cold-FET의 나머지 파라미터에 의해 모델링되는 Z-파라미터 사이의 잔차 오차를 최소화함으로써 HEMT의 모든 외인성 파라미터를 추출하는 기법을 제시한다. 제시된 기법을 사용하면 게이트와 드레인 모조패드의 추가적 제작 없이 게이트와 드레인 패드의 커패시턴스 값뿐 아니라 나머지 외인성 파라미터 값 모두를 성공적으로 추출할 수 있다.

• 한국전기전자재료학회논문지
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• 제28권4호
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• pp.218-221
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• 2015

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. In this study we have investigated a structure to reduce the on-resistance characteristics of the MOSFET. We have a proposed MOSFET structure of active cells region buried under the gate pad. The measurement are carried out with a EDS to analyze electrical characteristics, and the proposed MOSFET are compared with the conventional MOSFET. The result of proposed MOSFET was 1.68[${\Omega}$], showing 10% improvement compared to the conventional MOSFET at 700[V].

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.181-184
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• 1999

This paper presents the accurate deembeding method for pad and parasitics of MOSFET device. rad effects are deembedded using THRU LINE, which is much simpler method without laborious fitting procedure compared with conventional OPEN and SHORT pad modeling. Parasitic resistance extraction uses the algebraic relation between increments of inversion layer charge and oxide capacitance. It is especially adequate for insulating gate junction device. Extracted parasitics are verified through comparing modeled and measured S parameters.

• 한국전자통신학회논문지
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• 제8권11호
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• pp.1633-1640
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• 2013

본 논문에서는 이중게이트 FET를 고주파회로에 응용하기 위해 필요한 열잡음 파라미터를 추출하여 그 특성을 분석하였다. 이중게이트 열잡음 파라미터를 추출하기 위해 튜너를 이용해 잡음원의 임피던스를 바꿔가며 잡음특성을 측정하였으며, open과 short 더미를 이용해서 패드의 기생성분을 제거하였다. 측정결과 일반적인 캐스코드구조의 FET와 비교해서 5GHz에서 약 0.2dB의 잡음 개선효과가 있음을 확인하였으며, 시뮬레이션과 소신호 파라미터 분석을 통해 드레인 소스 및 드레인 게이트간 캐패시턴스의 감소에 의해 잡음지수가 줄어들었음을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.599-602
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• 2005

In this paper, we have performed a study that modifies the CPW Pad configurations to improve an $f_{max}$ characteristic of metamorphic HEMT. To analyze the CPW Pad structures of MHEMT, we use the ADS momentum simulator developed by $Agilent^{TM}$. Comparing the employed structure (G/W = 40/100 m), the optimized structure (G/W = 20/25 m) of CPW MHEMT shows the increased $S_{21}$ by 2.5 dB, which is one of the dominant parameters influencing the $f_{max}$ of MHEMT. To compare the performances of optimized MHEMT with the employed MHEMT, DC and RF characteristics of the fabricated MHEMT were measured. In the case of optimized CPW MHEMT, the measured saturated drain current density and transconductance $(g_m)$ were 693 mA/mm and 647 mS/mm, respectively. RF measurements were performed in a frequency range of $0.1{\sim}110$ GHz. A high $S_{21}$ gain of 5.5 dB is shown at a millimeter-wave frequency of 110 GHz. Two kinds of RF gains, $h_{21}$ and maximum available gain (MAG), versus the frequency, and a cut-off frequency ($f_t$) of ${\sim}154$ GHz and a maximum frequency of oscillation ($f_{max}$) of ${\sim}358$ GHz are obtained, respectively, from the extrapolation of the RF gains for a device biased at a peak transconductance. An optimized CPW MHEMT structure is one of the first reports among fabricated 0.1 m gate length MHEMTs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.545-545
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• 2008

Poly-Si is an essential material for floating gate in NAND Flash memory. To fabricate this material within region of floating gate, chemical mechanical polishing (CMP) is commonly used process for manufacturing NAND flash memory. We use colloidal silica abrasive with alkaline agent, polymeric additive and organic surfactant to obtain high Poly-Si to SiO2 film selectivity and reduce surface defect in Poly-Si CMP. We already studied about the effects of alkaline agent and polymeric additive. But the effect of organic surfactant in Poly-Si CMP is not clearly defined. So we will examine the function of organic surfactant in Poly-Si CMP with concentration separation test. We expect that surface roughness will be improved with the addition of organic surfactant as the case of wafering CMP. Poly-Si wafer are deposited by low pressure chemical vapor deposition (LPCVD) and oxide film are prepared by the method of plasma-enhanced tetra ethyl ortho silicate (PETEOS). The polishing test will be performed by a Strasbaugh 6EC polisher with an IC1000/Suba IV stacked pad and the pad will be conditioned by ex situ diamond disk. And the thickness difference of wafer between before and after polishing test will be measured by Ellipsometer and Nanospec. The roughness of Poly-Si film will be analyzed by atomic force microscope.

• 한국전기전자재료학회논문지
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• 제27권11호
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.