• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.747-750
• /
• 2003

We have studied PHEMTs optimization by means of fabrication of PHEMTs. All PHEMTs have been fixed with a gate length of 0.1 ${\mu}{\textrm}{m}$, a gate head size of 0.75${\mu}{\textrm}{m}$, and two gate fingers. We have measured the characteristics of PHEMTs with variation of source-drain spacing, pad size, and gate width. As a result, we have found the enhanced characteristics of $I_{dss}$, $S_{21}$, $h_{21}$, $f_{T}$, $f_{max}$, and $G_{ms}$ with increasing gate width. Also, $g_{m}$ has improved with decreasing source-drain spacing, and $S_{21}$ has improved with deceasing pad size.e.e.e.e.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.5
• /
• pp.117-126
• /
• 1989

In this paper, a new placement algorithm for gate array lay out design is proposed. The proposed algorithm can treat the variable-sized macrocells and by considering the I/Q pad locations, the routing between I/Q pads and the internal region of a chip can be automated effectively. The algorithm is composed of 3 parts. which are initial partitioning, initial placement and placement improvement. In the initial placement phase, a given circuit is partitioned into 5 sub-circuits, by clustering method with considers connectivities of cells not only with I/Q pads but also with related partitioned groups is used repeatedly to assign a unique position to each cell. In the placement improvement phase, the concept of probabilistic wiring density is introduced, and cell moving algorithm is proposed to make the density in a chip even.

• Journal of radiological science and technology
• /
• v.42 no.3
• /
• pp.175-180
• /
• 2019

In this study, we have researched the effectiveness of silicone pad. A distribution of scatter ray in mammography was evaluated using Monte-Carlo (MC) simulation technique and then a silicone pad was applied to remove the scatter ray for improving image quality. Molybdenum target and Molybdenum filter combination made a difference of 59.8% to a number of photon at 17.5 keV. On the other hand, Tungsten target and Rhodium filter showed a variation of 24.5% at 20 keV. Mean 68 of SNR was increased in Selenia and mean 1.04 of SNR was raised in Senographe. Silicone pad was significantly effective to reduce the scatter ray that was generated by primary X-ray. It can decrease an absorption rate of scatter ray to patient body and whilst it improve the image quality from increasing SNR.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.9 no.8
• /
• pp.853-859
• /
• 2014

This study presents a technique for extracting all the extrinsic parameters of HEMTs by minimizing the residual errors between a pinch-off cold-FET's gate and drain pad de-embedded Z-parameters and its modeled Z-parameters calculated by the cold-FET's remaining parameters. The presented technique allows us to successfully extract the remaining extrinsic parameter values as well as the gate and drain pad capacitance value without the additional fabrications of the gate and drain dummy pad.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.28 no.4
• /
• pp.218-221
• /
• 2015

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. In this study we have investigated a structure to reduce the on-resistance characteristics of the MOSFET. We have a proposed MOSFET structure of active cells region buried under the gate pad. The measurement are carried out with a EDS to analyze electrical characteristics, and the proposed MOSFET are compared with the conventional MOSFET. The result of proposed MOSFET was 1.68[${\Omega}$], showing 10% improvement compared to the conventional MOSFET at 700[V].

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.181-184
• /
• 1999

This paper presents the accurate deembeding method for pad and parasitics of MOSFET device. rad effects are deembedded using THRU LINE, which is much simpler method without laborious fitting procedure compared with conventional OPEN and SHORT pad modeling. Parasitic resistance extraction uses the algebraic relation between increments of inversion layer charge and oxide capacitance. It is especially adequate for insulating gate junction device. Extracted parasitics are verified through comparing modeled and measured S parameters.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.11
• /
• pp.1633-1640
• /
• 2013

In this paper, noise parameters for high frequency modeling of dual-gate FET are extracted and analyzed. To extract thermal noise parameter of dual gate, noise characteristics are measured by changing input impedance of noise source using Tuner, and the influence of pad parasitic elements are subtracted using open and short dummy structure. Measured results indicated that the dual-gate FET is improved the noise figure by 0.2dB compared with conventional cascode structure FET at 5GHz, and it confirmed that the noise figure has dropped due to reduction of capacitances between the drain and source, gate and drain by simulation and analysis of small-signal parameters.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.599-602
• /
• 2005

In this paper, we have performed a study that modifies the CPW Pad configurations to improve an $f_{max}$ characteristic of metamorphic HEMT. To analyze the CPW Pad structures of MHEMT, we use the ADS momentum simulator developed by $Agilent^{TM}$. Comparing the employed structure (G/W = 40/100 m), the optimized structure (G/W = 20/25 m) of CPW MHEMT shows the increased $S_{21}$ by 2.5 dB, which is one of the dominant parameters influencing the $f_{max}$ of MHEMT. To compare the performances of optimized MHEMT with the employed MHEMT, DC and RF characteristics of the fabricated MHEMT were measured. In the case of optimized CPW MHEMT, the measured saturated drain current density and transconductance $(g_m)$ were 693 mA/mm and 647 mS/mm, respectively. RF measurements were performed in a frequency range of $0.1{\sim}110$ GHz. A high $S_{21}$ gain of 5.5 dB is shown at a millimeter-wave frequency of 110 GHz. Two kinds of RF gains, $h_{21}$ and maximum available gain (MAG), versus the frequency, and a cut-off frequency ($f_t$) of ${\sim}154$ GHz and a maximum frequency of oscillation ($f_{max}$) of ${\sim}358$ GHz are obtained, respectively, from the extrapolation of the RF gains for a device biased at a peak transconductance. An optimized CPW MHEMT structure is one of the first reports among fabricated 0.1 m gate length MHEMTs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.545-545
• /
• 2008

Poly-Si is an essential material for floating gate in NAND Flash memory. To fabricate this material within region of floating gate, chemical mechanical polishing (CMP) is commonly used process for manufacturing NAND flash memory. We use colloidal silica abrasive with alkaline agent, polymeric additive and organic surfactant to obtain high Poly-Si to SiO2 film selectivity and reduce surface defect in Poly-Si CMP. We already studied about the effects of alkaline agent and polymeric additive. But the effect of organic surfactant in Poly-Si CMP is not clearly defined. So we will examine the function of organic surfactant in Poly-Si CMP with concentration separation test. We expect that surface roughness will be improved with the addition of organic surfactant as the case of wafering CMP. Poly-Si wafer are deposited by low pressure chemical vapor deposition (LPCVD) and oxide film are prepared by the method of plasma-enhanced tetra ethyl ortho silicate (PETEOS). The polishing test will be performed by a Strasbaugh 6EC polisher with an IC1000/Suba IV stacked pad and the pad will be conditioned by ex situ diamond disk. And the thickness difference of wafer between before and after polishing test will be measured by Ellipsometer and Nanospec. The roughness of Poly-Si film will be analyzed by atomic force microscope.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.27 no.11
• /
• pp.686-689
• /
• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.