• Journal of the Korean Vacuum Society
• /
• v.5 no.4
• /
• pp.327-332
• /
• 1996

In this study, the effects of $WSi_x$, thickness and fluorine concentration in tungsten polycide gate structure on gate oxide were investigated. As $WSi_x$, thickness increases, gate oxide thickness increases with fluorine incorporation in gate oxide, and time-to-breakdown($T_{BD,50%}$) of oxide decreases. The stress change with $WSi_x$ thickness was also examined. But it is understood that the dominant factor to degrade gate oxide properties is not the stress but the fluorine, incorporated during $WSi_x$ deposition, diffused into $WSiO_2$ after heat treatment. In order to understand the effect of fluorine diffusion into oxidem fluorine ion implanted gates were compared. The thickness variation and $T_{BD,50%}$ of gate oxide is saturated over 600 $\AA$ thickness of $WSi_x$. The TEM and SIMS studies show the microstructure less than 600 $\AA$ thickness is dense and flat in surface. However, over 600$\AA$, the microstructure of $WSi_x$ is divided into two parts: upper porous phase with rugged surface and lower dense phase with smmoth interface. And this upper phase is transformed into oxygen rich crystalline phase after annealing, and the fluorine is captured in this layer. Therefore, the fluorine diffusion into the gate oxide is saturated.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.970-973
• /
• 1999

When the size of the device is decreased, the hot carrier degradation presents a severe problem for long-term device reliability. In this paper we fabricated & tested the 0.26${\mu}{\textrm}{m}$ NMOSFET with wet gate oxide and nitride oxide gate to compare that the characteristics of hot carrier effect, charge to breakdown, transistor Id_Vg curve and charge trapping using the Hp4145 device tester As a result we find that the characteristics of nitride oxide gate device better than wet gate oxide device, especially a hot carrier lifetime(nitride oxide gate device satisfied 30years, but the lifetime of wet gate oxide was only 0.1year), variation of Vg, charge to breakdown and charge trapping etc.

• Korean Journal of Materials Research
• /
• v.3 no.6
• /
• pp.638-644
• /
• 1993

The degradation of dielectric breakdown field of 8nm-thick gate oxide ($SiO_2$) for Tipolycide MOS(meta1-oxide-semiconductor) capacitor with different annealing conditions and thickness of the polysilicon film on gate oxide was investigated. The degree of degradation in dielectric breakdown strength of the gate oxide for Ti-polycide gate became more severe with increasing annealing temperature and time, especially, for the case that thickness of the polysilicon film remained on the gate oxide after silicidation was reduced. The gate oxide degradation may be occurred by annealing although there is no direct contact of Ti-silicide with gate oxide. From SIMS analysis, it was confirmed that the degration of gate oxide during annealing was due to the diffusion of titanium atoms into the gate oxide film through polysilicon from the titanium silicide film.

• Transactions on Electrical and Electronic Materials
• /
• v.5 no.5
• /
• pp.169-172
• /
• 2004

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2004.05b
• /
• pp.658-660
• /
• 2004

In this paper, we have investigated electrical characteristics about doble gate MOSFET with changed oxide layer thickness of nam Sate and side gate, main gate and Si-substrate. We have known that optimum thickness of nam gate and side gate at 4nm, gate and Si-substrate at 3nm. We have applied for side gate voltage 3V, and drain voltage 1.5V. finally, we have known that importance of oxide layer thickness between main gate and Si-substrate better than main gate and side Sate.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.4
• /
• pp.799-804
• /
• 2016

To analyze the phenomenon of drain induced barrier lowering(DIBL) for top and bottom gate oxide thickness of asymmetric double gate MOSFET, the deviation of threshold voltage is investigated for drain voltage to have an effect on barrier height. The asymmetric double gate MOSFET has the characteristic to be able to fabricate differently top and bottom gate oxide thickness. DIBL is, therefore, analyzed for the change of top and bottom gate oxide thickness in this study, using the analytical potential distribution derived from Poisson equation. As a results, DIBL is greatly influenced by top and bottom gate oxide thickness. DIBL is linearly decreased in case top and bottom gate oxide thickness become smaller. The relation of channel length and DIBL is nonlinear. Top gate oxide thickness more influenced on DIBL than bottom gate oxide thickness in the case of high doping concentration in channel.

• The KIPS Transactions:PartA
• /
• v.15A no.4
• /
• pp.211-216
• /
• 2008

In this paper we fabricated and measured the $0.26{\mu}m$ NMOSFET with wet gate oxide and nitride oxide gate to compare that the charateristics of hot carrier effect, charge to breakdown, transistor Id_Vg curve, charge trapping, and SILC(Stress Induced Leakage Current) using the HP4145 device tester. As a result we find that the characteristics of nitride oxide gate device better than wet gate oxide device, especially hot carrier lifetime(nitride oxide gate device satisfied 30 years, but the lifetime of wet gate oxide was only 0.1 year), variation of Vg, charge to breakdown, electric field simulation and charge trapping etc.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.1
• /
• pp.41-45
• /
• 2012

We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.2
• /
• pp.63-68
• /
• 2003

The DC and RF characteristics of $In_{0.5}Ga_{0.5}P/In_{0.22}Ga_{0.78}As/GaAs$ p-HEMTs with a gate oxide layer of various thicknesses ($50{\;}{\AA},{\;}300{\;}{\AA}$) were investigated and compared with those of a Schottky-gate p-HEMT without the gate oxide layer. A prominent improvement in the breakdown voltage characteristics were observed for a p-HEMT having a gate oxide layer, which was implemented by using a liquid phase oxidation technique. The on-state breakdown voltage of the p-HEMT having the oxide layer of $50{\;}{\AA}$was ~2.3 times greater than that of a Schottky-gate p-HEMT. However, the p-HEMT having the gate oxide layer of $300{\;}{\AA}$ suffered from a poor gate-control capability due to the drain induced barrier lowering (DIBL) resulting from the thick gate oxide inspite of the lower gate leakage current and the higher on-state breakdown voltage. The results for a primitive p-HEMT having the gate oxide layer without any optimization of the structure and the process indicate the potential of p-HEMT having the gate oxide layer for high-power applications.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.41-44
• /
• 2000

Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.