• Proceedings of the Korean Society Of Semiconductor Equipment Technology
• /
• 2002.11a
• /
• pp.130-136
• /
• 2002

Device makers want to make higher density chips as devices shrink, especially WSix poly stack down is one of the key issues. However, EPD (End Point Detection) time delay was happened in DPS+ poly chamber which is a barrier to achieve device shrink because EPD time delay killed test pattern and next generation device. To investigate the EPD time delay, a test was done with patterned wafers. This experimental was carried out combined with OES(Optical Emission Spectroscopy) and SEM (Scanning Electron Microscopy). OES was used to find corrected wavelength in WSix stack down gate etching. SEM was used to confirm WSix gate profile and gate oxide damage. Through the experiment, a new wavelength (252nm) line of plasma is selected for DPS+ chamber to call correct EPD in WSix stack down gate etching for current device and next generation device.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.647-648
• /
• 2006

This paper presents the design results of peripheral circuits of non-volatile memory of nano floating gate cells. The designed peripheral circuits included command decoder, decoders, sense amplifiers and oscillator, which are targeted with 0.35um technology EEPROM process for operating test and reliable test. The simulation results show each operation and test mode of output voltage for word line, bit line, well and operating of sense amplifier.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
• /
• 2005.05a
• /
• pp.252-257
• /
• 2005

Injection molding is a very important industrial process for the manufacturing of plastics objects. During an injection molding process of composites, the fiber-matrix separation and fiber orientation are caused by the flow of molten polymer/fiber mixture. As a result, the product tends to be nonhomogeneous and anisotropic. Hence, it is very important to clarify the relations between separation' orientation and injection molding conditions. So far, there is no research on the measurement of fiber orientation using image processing. In this study, the effects of fiber content ratio and molding condition on the fiber orientation-angle distributions are studied experimentally. Using the image processing method, the fiber orientation distribution of weld-line in injection-molded products is assessed. And the effects of fiber content and injection mold-gate conditions on the fiber orientation are also discussed.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.7
• /
• pp.4411-4417
• /
• 2015

The proper design of the gate location for injection molding of plastic goods is obtained from three-dimensional injection molding analysis for various design alternatives. This paper is study on effect of gate location in injection molding. It have a decisive impact on productivity and quality of plastic goods. This objectives of this paper is to analysis effect of hot runner gate location for resin filling, weld line, injection pressure to manufacture of automobile air cleaner upper case with injection molding machine. Thus, to analysis these problems in this paper, location of gate are gave variety in 4 CASEs. In this paper, the CAE simulation considering each variations in location of gate is performed to predict the cause of faulty which appears in the injection molding process.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.5
• /
• pp.511-515
• /
• 2013

A Monte Carlo (MC) simulation study has been done in order to investigate the effects of line-edge-roughness (LER) induced by either 1P1E (single-patterning and single-etching) or 2P2E (double-patterning and double-etching) on fully-depleted silicon-on-insulator (FDSOI) tri-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Three parameters for characterizing the LER profile [i.e., root-mean square deviation (${\sigma}$), correlation length (${\zeta}$), and fractal dimension (D)] are extracted from the image-processed scanning electron microscopy (SEM) image for each photolithography method. It is experimentally verified that two parameters (i.e., ${\sigma}$ and D) are almost the same in each case, but the correlation length in the 2P2E case is longer than that in the 1P1E case. The 2P2E-LER-induced $V_TH$ variation in FDSOI tri-gate MOSFETs is smaller than the 1P1E-LER-induced $V_TH$ variation. The total random variation in $V_TH$, however, is very dependent on the other major random variation sources, such as random dopant fluctuation (RDF) and work-function variation (WFV).

• Proceedings of the KIEE Conference
• /
• 2005.07c
• /
• pp.2138-2139
• /
• 2005

We demonstrate a simple CO2 laser by controlling firing angle of a TRIAC switch in ac power line. The power supply for our laser system switches the voltage of the AC power line (60Hz) directly. The power supply does not need elements such as a rectifier bridge, energy-storage capacitors, or a current-limiting resistor in the discharge circuit. In order to control the laser output power, the pulse repetition rate is adjusted up to 60Hz and the firing angle of TRIAC gate is varied from 45 to 135. A ZCS(Zero Crossing Switch) circuit and a PIC one-chip microprocessor are used to control the gate signal of the TRIAC precisely. The maximum laser output of 40W is obtained at a total pressure of 18Torr, a pulse repetition rate of 60Hz, and a TRAIC gate firing angle of 90.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.10a
• /
• pp.611-613
• /
• 2016

The characteristics of tunnel field-effect transistor(TFET) structure with source-overlapped gate was investigated using a TCAD simulations. Tunneling is mostly divided into line-tunneling and point-tunneling, and line-tunneling is higher performance than point-tunneling in terms of subthreshold swing(SS) and on-current. In this paper, from the simulation results of source-overlapped gate length effects at silicon(Si), germanium(Ge), Si-Ge hetero TFET structure, the guideline of optimal structure with highest performance are proposed.

• Korean Chemical Engineering Research
• /
• v.49 no.1
• /
• pp.47-55
• /
• 2011

The optimum mold design and the optimum process condition were constructed upon executing process simulation of rubber injection molding with the commercial CAE program of MOLDFLOW (Ver. 5.2) in order to solve the process-problems of K company relating to cracks, which occurs at the inner cavity wall of C. V. joint boots. As a result it was confirmed that the real cracks occurs at the exactly same position of the cavity as exhibits the defects of weld and meld line and unsatisfactory curing according to the result of simulation. In order to prevent the occurrence of weld and meld line at the defect-position, the location of gate was altered to the optimum position of the cavity. Consequently the filling pattern was established to minimize the degree of the melt-fronts confronting or the melt-flows melding to prevent the occurrence of weld and meld line at the defect-position. It was observed that both gate-positions to maximize the degree of the formation of weld and meld line and air traps are located, respectively, in opposite direction each other with reference to the optimum gate position. In addition, the temperature of mold was raised by $10^{\circ}C$ and maintained at $170^{\circ}C$ for satisfactory curing.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.6
• /
• pp.137-143
• /
• 2015

A delay-line type time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) is most widely owing due to its simple structure and high conversion rate. However, the delay-line type TDC suffers from nonlinearity error caused by the long delay-line because its time interval measurement range is determined by the length of the used delay line. In this study, a new TDC structure with a shorter delay line by taking a pulse train as an input is proposed for improved time accuracy and efficient use of resources. The proposed TDC utilizes a pulse-train with four transitions and a transition state detector that identifies the used transition among four transitions and prevents the meta-stable state without a synchronizer. With 72 delay cells, the measured resolution and maximum non-linearity were 20.53 ps, and 1.46 LSB, respectively, and the time interval measurement range was 5070 ps which was enhanced by approximately 343 % compared to the conventional delay-line type TDC.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.5
• /
• pp.876-884
• /
• 2017

The current-voltage characteristics of Silicon(Si), Germanum(Ge), and hetero tunnel field-effect transistors(TFETs) with source-overlapped gate structure was investigated using TCAD simulations in terms of tunneling. A Si-TFET with gate oxide material $SiO_2$ showed the hump effects in which line and point tunneling appear simultaneously, but one with gate oxide material $HfO_2$ showed only the line tunneling due to decreasing threshold voltage and it shows better performance than one with gate oxide material $SiO_2$. Tunneling mechanism of Ge and hetero-TFETs with gate oxide material of both $SiO_2$ and $HfO_2$ are dominated by point tunneling, and showed higher leakage currents, and Si-TFET shows better performance than Ge and hetero-TFETs in terms of SS. These simulation results of Si, Ge, and hetero-TFETs with source-overlapped gate structure can give the guideline for optimal TFET structures with non-silicon channel materials.