• Journal of information and communication convergence engineering
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• v.5 no.2
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• pp.109-111
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• 2007

In this paper, MOS devices with ultrathin gate dielectrics (5.5 nm) are characterized and compared with those with conventional oxides particularly for nanoscale CMOS applications. Nitrogen concentrations and profiles in the nitride gate dielectrics were obtained that will play an important role in improving both hot-carrier lifetime and resistance to boron penetration. This approach seems very useful for future nanoscale CMOS device applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.278.1-278.1
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• 2014

Organic materials have been explored as the gate dielectric layers in thin film transistors (TFTs) of backplane devices for flexible display because of their inherent mechanical flexibility. However, those materials possess some disadvantages like low dielectric constant and thermal resistance, which might lead to high power consumption and instability. On the other hand, inorganic gate dielectrics show high dielectric constant despite their brittle property. In order to maintain advantages of both materials, it is essential to develop the alternative materials. In this work, we manufactured nanocomposite gate dielectrics composed of organic material and inorganic nanoparticle and integrated them into organic TFTs. For synthesis of nanocomposite gate dielectrics, polyimide (PI) was explored as the organic materials due to its superior thermal stability. Candidate nanoprticles (NPs) of halfnium oxide, titanium oxide and aluminium oxide were considered. In order to realize NP concentration dependent electrical characteristics, furthermore, we have synthesized the different types of nanocomposite gate dielectrics with varying ratio of each inorganic NPs. To analyze gate dielectric properties like the capacitance, metal-Insulator-metal (MIM) structures were prepared together with organic TFTs. The output and transfer characteristics of organic TFTs were monitored by using the semiconductor parameter analyzer (HP4145B), and capacitance and leakage current of MIM structures were measured by the LCR meter (B1500, Agilent). Effects of mechanical cyclic bending of 200,000 times and thermally heating at $400^{\circ}C$ for 1 hour were investigated to analyze mechanical and thermal stability of nanocomposite gate dielectrics. The results will be discussed in detail.

• Ceramist
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• v.9 no.4
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• pp.58-71
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• 2006

Scaling of the gate stack has been one of the major contributors to the performance enhancement of CMOSFET devices in past technology generations. The scalability of gate stack has diminished in recent years and alternative gate stack technology such as metal electrode and high-k dielectrics has been intensively studied during the last decade. Tody the performance of high-k dielectrics almost matches that of conventional $SiO_2-based$ gate dielectrics. However, many technical challenges remain to be resolved before alternative gate stacks can be introduced into mainstream technology. This paper reviews the research in alternative gate stack technologies to provide insights for future research.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.312-314
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• 2009

We have fabricated pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics. The gate dielectrics is composed of PVP, poly[melamine-coformaldehyde] (PMF) and photo-initiator [1-phenyl-2-hydroxy-2-methylpropane-1-one, Darocur1173]. By adding small amount (1 %) of photo-initiator, the cross-linking temperature is lowered to $115^{\circ}C$, which is lower than general thermal curing reaction temperature of cross-linked PVP (> $180^{\circ}C$). The hysteresis and the leakage current of the OTFTs are also decreased by adding the PMF and the photoinitiator in PVP gate dielectrics.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.252-255
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• 2013

Nano MOS with $Er_2O_3/SiO_2$ double-layer gate dielectrics was demonstrated by EDISON Nanophysics software. Double-layer structure decreases the gate leakage current in two orders compared with $SiO_2$ single-layer gate dielectric.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.93-94
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• 2005

본 연구에서는 저온 공정에서 제작되는 소자에의 응용을 위하여 Inductively Coupled Plasma Chemical Vapor Deposition(ICP-CVD) 내에서 $N_2O$ 기체를 활용한 plasma oxidation을 통한 silicon 표면의 oxynitridation과 이로부터 tunnel gate dielectirics로 사용될 SiON 층을 형성하였으며, 형성된 SiOxNy 층의 전기적 특성을 측정하여 tunnel gate dielectrics로서 효과적인 기능을 수행함을 확인하였다. 형성된 박막의 성분 분석을 위하여 energy dispersive spectroscopy(EDS)를 이용하여 SiOxNy 층의 생성을 확인하였으며, 전기적인 특성을 통하여 tunnel gate dielectrics의 기능을 수행함을 알 수 있었다. 형성된 SiOxNy 층은 초박막 형태임에도 절연막으로서의 기능을 나타내었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.301.2-301.2
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• 2016

Metal-oxide thin-film transistors (TFTs) have gained a considerable interest in transparent electronics owing to their high optical transparency and outstanding electrical performance even in an amorphous state. Also, these metal-oxide materials can be solution-processed at a low temperature by using deep ultraviolet (DUV) induced photochemical activation allowing facile integration on flexible substrates [1]. In addition, high-dielectric constant (k) inorganic gate dielectrics are also of a great interest as a key element to lower the operating voltage and as well as the formation of coherent interface with the oxide semiconductors, which may lead to a considerable improvement in the TFT performance. In this study, we investigated the electrical properties of solution-processed high-k strontium-doped AlOx (Sr-AlOx) gate dielectrics. Using the Sr-AlOx as a gate dielectric, indium-gallium-zinc oxide (IGZO) TFTs were fabricated and their electrical properties are analyzed. We demonstrate IGZO TFTs with a 10-nm-thick Sr-AlOx gate dielectric which can be operated at a low voltage (~5 V).

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.17 no.5
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• pp.187-191
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• 2007

The device performance of ZnO-thin film transistors(ZnO-TFTs) with gate dielectrics of $SiO_2,\;SiN_x$ and Polyvinylphenol(PVP) having a bottom gate configuration were investigated. ZnO-TFTs can induce high device performance with low intrinsic carrier concentration of ZnO only by controlling gas flow rates without additional doping or annealing processes. The field effect mobility and on/off ratio of ZnO-TFTs with $SiN_x$ were $20.2cm^2V^{-1}s^{-1}\;and\;5{\times}10^6$ respectively which is higher than those previously reported. The device adoptable values of the mobility of $1.37cm^2V^{-1}s^{-1}$ and the on/off ratio of $6{\times}10^3$ were evaluated from the device with organic PVP dielectric.

• Macromolecular Research
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• v.17 no.6
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• pp.436-440
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• 2009

We improved the performance of pentacene-based thin film transistors by changing the curing environment of poly(4-vinylphenol) (PVP) gate dielectrics, while keeping the dielectric constant the same. The field-effect mobility of the pentacene TFTs constructed using the vacuum cured PVP was higher than that of the device based on the Ar flow cured gate dielectric, possibly due to the higher crystalline perfection of the pentacene films. The present results demonstrated that the curing conditions used can markedly affect the surface energy of polymer gate dielectrics, thereby affecting the field-effect mobility of TFTs based on those dielectrics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1771-1777
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• 2016

In this thesis, the breakdown voltage characteristics of silicon nanowire N-channel GAA MOSFETs were analyzed through experiments and 3-dimensional device simulation. GAA MOSFETs with the gate length of 250nm, the gate dielectrics thickness of 6nm and the channel width ranged from 400nm to 3.2um were used. The breakdown voltage was decreased with increasing gate voltage but it was increased at high gate voltage. The decrease of breakdown voltage with increasing channel width is believed due to the increased current gain of parasitic transistor, which was resulted from the increased potential in channel center through floating body effects. When the positive charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was decreased due to the increased potential in channel center. When the negative charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was increased due to the decreased potential in channel center. We confirmed that the measurement results were agreed with the device simulation results.