• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.304.2-304.2
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• 2016

Hafnium oxide-aluminum oxide (HfO2-Al2O3) dielectric films have been fabricated by Pulsed Laser Deposition (PLD), and their properties are studied in comparison with HfO2 films. As a gate dielectric of the TFT, in spite of its high dielectric constant, HfO2 has a small energy band gap and microcrystalline structure with rough surface characteristics. When fabricated by the device, it has the drawback of generating a high leakage current. In this study, the HfAlO films was obtained by Pulsed Laser Deposition with HfO2-Al2O3 target(chemical composition of (HfO2)86wt%(Al2O3)14wt%). The characteristics of the thin Film have been investigated by x-ray diffraction (XRD), atomic force microscopy (AFM) and spectroscopic ellipsometer (SE) analyses. The X-ray diffraction studies confirmed that the HfAlO has amorphous structure. The RMS value can be compared to the surface roughness via AFM analysis, it showed HfAlO thin Film has more lower properties than HfO2. The energy band gap (Eg) deduced by spectroscopic ellipsometer was increased. HfAlO films was expected to improved the interface quality between channel and gate insulator. Apply to an oxide thin Film Transistors, HfAlO may help improve the properties of device.

• 전자공학회논문지
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• 제50권6호
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• pp.85-90
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• 2013

본 논문에서는 본 연구실에서 제안된 Dummy Gate Assisted MOSFET을 이용하여 6bit SAR (Successive Approximation Register) ADC를 설계하였으며 이에 대한 대조군으로 Conventional MOSFET으로 동일한 회로를 설계하여 두 회로의 Co-60 Gamma Ray에 의한 누적방사선 영향을 비교 분석해 보았다. 설계된 SAR ADC는 Binary Capacitor DAC과 Dynamic Latch 형태의 Comparator 그리고 Logic으로 구성이 되었으며, 0.35um standard CMOS공정으로 제작되었다. 방사선 조사 후 Conventional MOSFET을 이용한 ADC는 정상동작하지 못하였지만, Dummy Gate Assisted MOSFET을 사용한 ADC는 방사선 조사 후 DNL은 0.7LSB에서 2.0LSB, INL은 1.8LSB에서 3.2LSB로 다소 증가하였으나 정상적인 A/D 변환이 가능하다는 것을 확인하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.615-624
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• 2014

In this paper, we explore the electrical properties and high-frequency performance of carbon nanotube field-effect transistors (CNTFETs), based on the non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. The calculated results show that CNTFETs exhibit superior performance compared with graphene nanoribbon field-effect transistors (GNRFETs), such as better control ability of the gate on the channel, higher drive current with lower subthreshold leakage current, and lower subthreshold-swing (SS). Due to larger band-structure-limited velocity in CNTFETs, ballistic CNTFETs present better high-frequency performance limit than that of Si MOSFETs. The parameter effects of CNTFETs are also investigated. In addition, to enhance the immunity against short - channel effects (SCE), hetero - material - gate CNTFETs (HMG-CNTFETs) have been proposed, and we present a detailed numerical simulation to analyze the performances of scaling down, and conclude that HMG-CNTFETs can meet the ITRS'10 requirements better than CNTs.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.154-154
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• 2012

Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

• 한국전기전자재료학회논문지
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• 제31권6호
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• pp.372-376
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• 2018

The effects of off-state bias stress on the characteristics of p-type poly-Si TFT were investigated. To reduce the gate-induced drain leakage (GIDL) current, the off-state bias stress was changed by varying Vgs and Vds. After application of the off-state bias stress, the Vgs causing GIDL current was dramatically increased from 1 to 10 V, and thus, the Vgs margin to turn off the TFT was improved. The on-current and subthreshold swing in the aged TFT was maintained. We performed a technology computer-aided design (TCAD) simulation to describe the aged characteristics. The aged-transfer characteristics were well described by the local charge trapping. The activation energy of the GIDL current was measured for the pristine and aged characteristics. The reduced GIDL current was mainly a thermionic field-emission current.

• 전자공학회논문지
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• 제50권7호
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• pp.102-108
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• 2013

용액 공정 기반으로 유기 전자소자를 제작할 시, 회전 도포 방법을 이용하는데 이 방법의 단점 중의 하나는 후속 회전 도포할 때 용액 속의 용매에 의해 이미 제작된 유기 박막을 물리적 또는 화학적인 손상을 입힐 수 있다는 것이다. 이러한 문제들로 인해 후속적인 박막 제조에 사용될 수 있는 용매의 종류는 매우 제한적일 수 밖에 없다. 본 논문에서는 기존에 알려진 용매들의 적절한 조합으로 인해 다층 박막 제작이 가능함을 보이고, 이를 이용하여 용액 공정 기반 유기 트랜지스터를 제작하여 성능의 향상을 보일 것이다. 트랜지스터의 구조는 하부 게이트 하부 접촉 (bottom gate, bottom contact) 구조로 제작되었고 게이트 절연체는 강유전체 고분자로 제작되었는데 한 번의 회전 도포 방법과 두 번의 회전 도포 방법으로 동일 두께를 형성하여 두 트랜지스터를 제작, 드레인 전압에 따른 소스-드레인 전류를 비교하였다. 그 결과 소스-게이트 누설 전류 감소 효과가 있었고, ON 상태에서의 소스-드레인 전류의 상승효과도 관찰되었다. 전류-전압 그래프로부터 계산된 이동도는 약 2.7배 증가되었다. 그러므로 용액 공정 기반 전계효과 트랜지스터를 제작할 시, 게이트 절연체를 다층 구조로 제작하면 성능 향상에 이점이 많다는 것을 알 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.319-322
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• 2003

To match the charge induced by the insulators $CeO_2$ with the remanent polarization of ferro electric SBT thin films, areas of Pt/SBT/Pt (MFM) and those of $Pt/CeO_2/Si$ (MIS) capacitors were ind ependently designed. The area $S_M$ of MIS capacitors to the area $S_F$ of MFM capacitors were varied from 1 to 10, 15, and 20. Top electrode Pt and SBT layers were etched with for various area ratios of $S_M\;/\;S_F$. Bottom electrode Pt and $CeO_2$ layers were respectively deposited by do and rf sputtering in-situ process. SBT thin film were prepared by the metal orgnic decomposition (MOD) technique. $Pt(100nm)/SBT(350nm)/Pt(300nm)/CeO_2(40nm)/p-Si$ (MFMIS) gate structures have been fabricated with the various $S_M\;/\;S_F$ ratios using inductively coupled plasma reactive ion etching (ICP-RIE). The leakage current density of MFMIS gate structures were improved to $6.32{\times}10^{-7}\;A/cm^2$ at the applied gate voltage of 10 V. It is shown that in the memory window increase with the area ratio $S_M\;/\;S_F$ of the MFMIS structures and a larger memory window of 3 V can be obtained for a voltage sweep of ${\pm}9\;V$ for MFMIS structures with an area ratio $S_M\;/\;S_F\;=\;6$ than that of 0.9 V of MFS at the same applied voltage. The maximum memory windows of MFMIS structures were 2.28 V, 3.35 V, and 3.7 V with the are a ratios 1, 2, and 6 at the applied gate voltage of 11 V, respectively. It is concluded that ferroelectric gate capacitors of MFMIS are good candidates for nondestructive readout-nonvolatile memories.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.80-81
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• 2008

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than $10^5$. Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.