• 제목/요약/키워드: Gate Insulator

검색결과 380건 처리시간 0.028초

Solution-Processed Inorganic Thin Film Transistors Fabricated from Butylamine-Capped Indium-Doped Zinc Oxide Nanocrystals

  • Pham, Hien Thu;Jeong, Hyun-Dam
    • Bulletin of the Korean Chemical Society
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    • 제35권2호
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    • pp.494-500
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    • 2014
  • Indium-doped zinc oxide nanocrystals (IZO NCs), capped with stearic acid (SA) of different sizes, were synthesized using a hot injection method in a noncoordinating solvent 1-octadecene (ODE). The ligand exchange process was employed to modify the surface of IZO NCs by replacing the longer-chain ligand of stearic acid with the shorter-chain ligand of butylamine (BA). It should be noted that the ligand-exchange percentage was observed to be 75%. The change of particle size, morphology, and crystal structures were obtained using a field emission scanning electron microscope (FE-SEM) and X-ray diffraction pattern results. In our study, the 5 nm and 10 nm IZO NCs capped with stearic acid (SA-IZO) were ligand-exchanged with butylamine (BA), and were then spin-coated on a thermal oxide ($SiO_2$) gate insulator to fabricate a thin film transistor (TFT) device. The films were then annealed at various temperatures: $350^{\circ}C$, $400^{\circ}C$, $500^{\circ}C$, and $600^{\circ}C$. All samples showed semiconducting behavior and exhibited n-channel TFT. Curing temperature dependent on mobility was observed. Interestingly, mobility decreases with the increasing size of NCs from 5 to 10 nm. Miller-Abrahams hopping formalism was employed to explain the hopping mechanism insight our IZO NC films. By focusing on the effect of size, different curing temperatures, electron coupling, tunneling rate, and inter-NC separation, we found that the decrease in electron mobility for larger NCs was due to smaller electronic coupling.

Controlled Synthesis of Hexagonal Boron Nitride on Cu Foil Using Chemical Vapor Deposition

  • Han, Jaehyun;Lee, Jun-Young;Kwon, Heemin;Yeo, Jong-Souk
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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    • pp.630-630
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    • 2013
  • Recently, atomically smooth hexagonal boron nitride(h-BN) known as a white graphene has drawn great attention since the discovery of graphene. h-BN is a III-V compound and has a honeycomb structure very similar to graphene with smaller lattice mismatch. Because of strong covalent sp2bonds like graphene, h-BN provides a high thermal conductivity and mechanical strength as well as chemical stability of h-BN superior to graphene. While graphene has a high electrical conductivity, h-BN has a highly dielectric property as an insulator with optical band gap up to 6eV. Similar to the graphene, h-BN can be applied to a variety of field, such as gate dielectric layers/substrate, ultraviolet emitter, transparent membrane, and protective coatings. However, up until recently, obtaining and controlling good quality monolayer h-BN layers have been too difficult and challenging. In this work, we investigate the controlled synthesis of h-BN layers according to the growth condition, time, temperature, and gas partial pressure. h-BN is obtained by using chemical vapor deposition on Cu foil with ammonia borane (BH3NH3) as a source for h-BN. Scanning Transmission Electron Microscopy (STEM, JEOL-JEM-ARM200F) is used for imaging and structural analysis of h-BN layer. Sample's surface morphology is characterized by Field emission scanning electron microscopy (SEM, JEOL JSM-7100F). h-BN is analyzed by Raman spectroscopy (HORIBA, ARAMIS) and its topographic variations by Atomic force microscopy (AFM, Park Systems XE-100).

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Low-temperature crystallization of high-dielectric (Ba,Sr)$TiO_3$ thin films for embedded capacitors

  • Cho, Kwang-Hwan;Kang, Min-Gyu;Kang, Chong-Yun;Yoon, Seok-Jin
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2010년도 춘계학술회의 초록집
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    • pp.21-21
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    • 2010
  • (Ba,Sr)$TiO_3$ (BST) thin film with a perovskite structure has potential for the practical application in various functional devices such as nonvolatile-memory components, capacitor, gate insulator of thin-film transistors, and electro-optic devices for display. Normally, the BST thin films derived from sol-gel and sputtering are amorphous or partially crystalline when processed below $600^{\circ}C$. For the purpose of integrating BST thin film directly into a Si-based read-out integrated circuit (ROIC), it is necessary to process the BST film below $400^{\circ}C$. The microstructural and electrical properties of low-temperature crystallized BST film were studied. The BST thin films have been fabricated at $350^{\circ}C$ by UV-assisted rapidly thermal annealing (RTA). The BST films are in a single perovskite phase and have well-defined electrical properties such as high dielectric constant, low dielectric loss, low leakage current density, and high breakdown voltage. Photoexcitation of the organics contained in the sol-gel-derived films by high-intensity UV irradiation facilitates elimination of the organics and formation of the single-crystalline phase films at low temperatures. The amorphous BST thin film was transformed to a highly (h00)-oriented perovskite structure by high oxygen pressure processing (HOPP) at as low as $350^{\circ}C$. The dielectric properties of BST film were comparable to (or even better than) those of the conventionally processed BST films prepared by sputtering or post-annealing at temperature above $600^{\circ}C$. When external pressure was applied to the well-known contractive BST system during annealing, the nucleation energy barrier was reduced; correspondingly, the crystallization temperature decreased. The UV-assisted RTA and HOPP, as compatible with existing MOS technology, let the BST films be integrated into radio-frequency circuit and mixed-signal integrated circuit below the critical temperature of $400^{\circ}C$.

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플렉서블 디스플레이의 적용을 위한 저온 실리콘 질화물 박막성장의 특성 연구 (The Characteristics of Silicon Nitride Films Grown at Low Temperature for Flexible Display)

  • 임노민;김문근;권광호;김종관
    • 한국전기전자재료학회논문지
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    • 제26권11호
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    • pp.816-820
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    • 2013
  • We investigated the characteristics of the silicon oxy-nitride and nitride films grown by plasma-enhanced chemical vapor deposition (PECVD) at the low temperature with a varying $NH_3/N_2O$ mixing ratio and a fixed $SiH_4$ flow rate. The deposition temperature was held at $150^{\circ}C$ which was the temperature compatible with the plastic substrate. The composition and bonding structure of the nitride films were investigated using Fourier transform infrared spectroscopy (FTIR) and X-ray photoelectron spectroscopy (XPS). Nitrogen richness was confirmed with increasing optical band gap and increasing dielectric constant with the higher $NH_3$ fraction. The leakage current density of the nitride films with a high NH3 fraction decreased from $8{\times}10^{-9}$ to $9{\times}10^{-11}(A/cm^2$ at 1.5 MV/cm). This results showed that the films had improved electrical properties and could be acceptable as a gate insulator for thin film transistors by deposited with variable $NH_3/N_2O$ mixing ratio.

영상센서를 위한 비정질 실리콘 박막트랜지스터의 제작 및 특성 (Fabrication and Characteristics of a-Si : H TFT for Image Sensor)

  • 김영진;박욱동;김기완;최규만
    • 센서학회지
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    • 제2권1호
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    • pp.95-99
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    • 1993
  • 영상 센서를 위한 비정질 실리콘 박막트랜지스터 (a-Si : HTFT)를 제작하고 그 동작 특성 을 조사하였다. 게이트 절연막으로는 비정질 실리콘 질화막(a-SiN : H)을 증착하였으며 소오스와 드레인 영역에서의 저항성 접합을 위해 $n^{+}$ 형 비정질 실리콘($n^{+}$-a-Si : H)을 증착하였다. 이 때 a-SiN : H막과 a-Si : H막의 두께는 각각 $2000{\AA}$, $n^{+}$-a-Si : H막의 두께는 $500{\AA}$이었다. 또한 a-Si : H TFT의 채널길이와 채널폭은 각각 $50{\mu}m$$1000{\mu}m$였다. 본 연구에서 제작한 a-Si : H TFT의 ON/OFF 전류비는 $10^{5}$, 문턱전압은 6.3 V 그리고 전계효과 이동도는 $0.15cm^{2}/V{\cdot}s$로 나타났다.

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나노결정 InGaZnO 산화물 박막트랜지스터와 비결정 InGaZnO 산화물 박막트랜지스터의 소자 신뢰성에 관한 비교 연구 (Comparison of Stability on the Nano-crystalline Embedded InGaZnO and Amorphous InGaZnO Oxide Thin-film Transistors)

  • 신현수;안병두;임유승;김현재
    • 한국전기전자재료학회논문지
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    • 제24권6호
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    • pp.473-479
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    • 2011
  • In this paper, we have compared amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) with the nano-crystalline embedded-IGZO ($N_c$-embedded-IGZO) TFT fabricated by solid-phase crystallization (SPC) technique. The field effect mobility (${\mu}_{FE}$) of $N_c$-embedded-IGZO TFT was 2.37 $cm^2/Vs$ and the subthreshold slope (S-factor) was 0.83 V/decade, which showed lower performance than those of a-IGZO TFT (${\mu}_{FE}$ of a-IGZO was 9.67 $cm^2/Vs$ and S-factor was 0.19 V/decade). This results originated from generation of oxygen vacancies in oxide semiconductor and interface between gate insulator and semiconductor due to high temperature annealing process. However, the threshold voltage shift (${\Delta}V_{TH}$) of $N_c$-embedded-IGZO TFT was 0.5 V, which showed 1 V less shift than that of a-IGZO TFT under constant current stress during $10^5$ s. This was because there were additionally less increase of interface trap charges in Nc-embedded-IGZO TFT than a-IGZO TFT.

비정질 인듐-갈륨-아연 산화물 기반 박막 트랜지스터의 NBIS 불안정성 개선을 위한 연구동향 (Research Trends for Improvement of NBIS Instability in Amorphous In-Ga-ZnO Based Thin-Film Transistors)

  • 윤건주;박진수;김재민;조재현;배상우;김진석;김현후;이준신
    • 한국전기전자재료학회논문지
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    • 제32권5호
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    • pp.371-375
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    • 2019
  • Developing a thin-film transistor with characteristics such as a large area, high mobility, and high reliability are key elements required for the next generation on displays. In this paper, we have investigated the research trends related to improving the reliability of oxide-semiconductor-based thin-film transistors, which are the primary focus of study in the field of optical displays. It has been reported that thermal treatment in a high-pressure oxygen atmosphere reduces the threshold voltage shift from -7.1 V to -1.9 V under NBIS. Additionally, a device with a $SiO_2/Si_3N_4$ dual-structure has a lower threshold voltage (-0.82 V) under NBIS than a single-gate-insulator-based device (-11.6 V). The dual channel structure with different oxygen partial pressures was also confirmed to have a stable threshold voltage under NBIS. These can be considered for further study to improve the NBIS problem.

고 출력 응용을 위한 2개의 전송영점을 가지는 최소화된 SOI CMOS 가변 대역 통과 여파기 (SOI CMOS Miniaturized Tunable Bandpass Filter with Two Transmission zeros for High Power Application)

  • 임도경;임동구
    • 전자공학회논문지
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    • 제50권1호
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    • pp.174-179
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    • 2013
  • 이 논문에서는 multiple split ring resonator(MSRRs)와 로딩된 스위치드 제어부를 이용하여 2개의 전송영점을 가지는 대역통과 여파기를 설계하였다. 높은 선택도와 칩 사이즈의 초소형화를 위해 비대칭의 급전 선로를 도입하여 통과 대역 주위에 위치한 전송 영점 쌍을 생성하였다. Cross coupling 또는 source-load coupling 방식을 이용한 기존의 여파기와 비교해보면 이 논문에서 제안된 여파기는 단지 2개의 공진기만으로 전송 영점을 생성하여 높은 선택도를 얻었다. 여파기의 선택도와 민감도(삽입 손실)를 최적화하기 위해 비대칭 급전 선로의 위치에 따른 전송 영점과 삽입손실의 관계를 분석하였다. 통과 대역 주파수의 가변과 30dBm 정도의 고 출력 신호를 처리하기 위해 MSRRs의 최 외각 링에 MIM 커패시터와 stacked-FET으로 구성된 SOI-CMOS 스위치드 제어부가 로딩되어 있다. 스위칭 트랜지스터의 전원을 켜고 끔으로써 통과 대역 주파수를 4GHz로부터 5GHz까지 이동시킬 수 있다. 제안된 칩 여파기는 0.18-${\mu}m$ SOI CMOS 기술을 이용함으로써 높은 Q를 가지는 수동 소자와 stacked-FET의 집적을 가능하게 만들었다. 설계된 여파기는 $4mm{\times}2mm$ ($0.177{\lambda}g{\times}0.088{\lambda}g$)의 초소형화 된 크기를 가진다. 여기서 ${\lambda}g$는 중심 주파수에서의 $50{\Omega}$ 마이크로스트립 선로의 관내 파장을 나타낸다. 측정된 삽입손실(S21)은 5.4GHz, 4.5GHz에서 각 각 5.1dB, 6.9dB를 나타내었다. 설계된 여파기는 중심 주파수로부터 500MHz의 오프셋에서 20dB이상의 대역외 저지 특성을 나타내었다.

Integration of the 4.5

  • Lee, Sang-Yun;Koo, Bon-Won;Jeong, Eun-Jeong;Lee, Eun-Kyung;Kim, Sang-Yeol;Kim, Jung-Woo;Lee, Ho-Nyeon;Ko, Ick-Hwan;Lee, Young-Gu;Chun, Young-Tea;Park, Jun-Yong;Lee, Sung-Hoon;Song, In-Sung;Seo, O-Gweon;Hwang, Eok-Chae;Kang, Sung-Kee;Pu, Lyoung-Son;Kim, Jong-Min
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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    • pp.537-539
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    • 2006
  • We developed an 4.5" $192{\times}64$ active matrix organic light-emitting diode display on a glass using organic thin-film transistor (OTFT) switching-arrays with two transistors and a capacitor in each sub-pixel. The OTFTs has bottom contact structure with a unique gate insulator and pentacene for the active layer. The width and length of the switching OTFT is $800{\mu}m$ and $10{\mu}m$ respectively and the driving OTFT has $1200{\mu}m$ channel width with the same channel length. On/off ratio, mobility, on-current of switching OTFT and on-current of driving OTFT were $10^6,0.3{\sim}0.5\;cm^2/V{\cdot}sec$, order of 10 ${\mu}A$ and over 100 ${\mu}A$, respectively. AMOLEDs composed of the OTFT switching arrays and OLEDs made using vacuum deposition method were fabricated and driven to make moving images, successfully.

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핫픽업 전사기술을 이용한 고성능 WSe2 기반 전계효과 트랜지스터의 제작 (High-performance WSe2 field-effect transistors fabricated by hot pick-up transfer technique)

  • 김현호
    • 접착 및 계면
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    • 제21권3호
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    • pp.107-112
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    • 2020
  • 원자층 두께의 전이금속 칼코겐화합물(transition-metal dichalcogenide, TMD) 기반 반도체 소재는 그래핀과 비슷한 구조의 이차원구조를 지니는 소재로서 조절 가능한 밴드갭 뿐만 아니라 우수한 유연성, 투명성 등 다양한 장점으로 인해 다양한 미래사회의 전자소자에 활용될 수 있는 소재로서 각광받고 있다. 하지만 이러한 TMD 소재들은 수분과 산소에 매우 취약하다는 단점 때문에 대기안정성을 해결할 수 있는 다양한 시도가 이루어지고 있다. 본 연구에서는 핫픽업 전사기술을 이용하여 TMD 반도체 소재 중 하나인 WSe2 와 이차원 절연체 h-BN와의 수직 헤테로 구조를 제작하여 WSe2의 대기 안정성을 향상시키기 위한 연구를 수행하였으며, h-BN/WSe2 구조를 활용하여 WSe2 기반 고성능 전계효과 트랜지스터 제작에 대한 연구를 수행하였다. 제작된 소자의 전기적 특성을 분석한 결과, h-BN에 의해 표면이 안정화된 WSe2 기반 소자는 대기안정성 뿐만 아니라 150 ㎠/Vs의 상온 정공 이동도, 3×106의 온/오프 전류비, 192 mV/decade의 서브문턱스윙 등 우수한 전기적 특성을 갖는다는 것 또한 확인할 수 있었다.