• Journal of Information Display
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• 제12권1호
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• pp.47-50
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• 2011

Highly stable amorphous indium.gallium.zinc-oxide (a-IGZO) thin-film transistors (TFTs) were fabricated with an etchstopper and via-hole structure. The TFTs exhibited 40 $cm^2$/V s field-effect mobility and a 0.21 V/dec gate voltage swing. Gate-bias stress induced a negligible threshold voltage shift (${\Delta}V_{th}$) at room temperature. The excellent stability is attribute to the via-hole and etch-stopper structure, in which, the source/drain metal contacts the active a-IGZO layer through two via holes (one on each side), resulting in minimized damage to the a-IGZO layer during the plasma etching of the source/drain metal. The comparison of the effects of the DC and AC stress on the performance of the TFTs at $60^{\circ}C$ showed that there was a smaller ${\Delta}V_{th}$ in the AC stress compared with the DC stress for the same effective stress time, indicating that the trappin of the carriers at the active layer-gate insulator interface was the dominant degradation mechanism.

• 한국전기전자재료학회논문지
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• 제33권4호
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• pp.286-290
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• 2020

The formation of inorganic thin films in low-temperature solution processes is necessary for a wide range of commercial applications of organic electronic devices. Aluminum oxide thin films can be utilized as barrier films that prevent the deterioration of an electronic device due to moisture and oxygen in the air. In addition, they can be used as the gate insulating layers of a thin film transistor. In this study, aluminum oxide thin film were formed using two methods simultaneously, a thermal process and the DUV process, and the properties of the thin films were compared. The result of converting aluminum nitrate hydrate to aluminum oxide through a hybrid process using a thermal treatment and DUV was confirmed by XPS measurements. A film-based a-IGZO TFT was fabricated using the formed inorganic thin film as a gate insulating film to confirm its properties.

• 반도체디스플레이기술학회지
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• 제16권2호
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• pp.66-69
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• 2017

In this paper, solution based Indium Zinc Oxide thin film transistors (IZO TFTs) were fabricated with PVP gate dielectric. To enhance the electrical properties, UV-O3 treatment is proposed on solution based IZO TFTs. The gate leakage current and interface trap density is compatible with conventional ZnO-based TFT with inorganic gate insulator. Especially, the UV-treated device shows improved electrical characteristics compared to the untreated device. These results can be explained by X-ray photoelectron spectroscopy (XPS) analysis, which shows that the oxygen vacancy of UV-O3 treatment is higher than that of no treatment.

• 센서학회지
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• 제28권2호
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• pp.76-80
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• 2019

The characteristics of a titanium oxide layer prepared using a plasma electrolytic oxidation (PEO) process were investigated, using an extended gate ion sensitive field effect transistor (EG-ISFET) to confirm the layer's capability to react with hydrogen ions. The surface morphology and element distribution of the PEO-processed titanium oxide were observed and analyzed using field-emission scanning-electron microscopy (FE-SEM) and energy-distribution spectroscopy (EDS). The titanium oxide prepared by the PEO process was utilized as a hydrogen-ion sensing membrane and an extended gate insulator. A commercially available n-channel enhancement MOS-FET (metal-oxide-semiconductor FET) played a role as a transducer. The responses of the PEO-processed titanium oxide to different pH solutions were analyzed. The output drain current was linearly related to the pH solutions in the range of pH 4 to pH 12. It was confirmed that the titanium-oxide layer prepared by the PEO process could feasibly be used as a hydrogen-ion-sensing membrane for EGFET measurements.

• Current Applied Physics
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• 제18권12호
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• pp.1546-1552
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• 2018

The polymer nanocomposite as a gate dielectric film was prepared via sol-gel method. The formation of crosslinked structure among nanofillers and polymer matrix was proved by Fourier transform infrared spectroscopy (FT-IR). Differential thermal analysis (DTA) results showed significant increase in the thermal stability of the nanocomposite with respect to that of pure polymer. The nanocomposite films deposited on the p- and n-type Si substrates formed very smooth surface with rms roughness of 0.045 and 0.058 nm respectively. Deconvoluted $Si_{2s}$ spectra revealed the domination of the Si-OH hydrogen bonds and Si-O-Si covalence bonds in the structure of the nanocomposite film deposited on the p- and n-type Si semiconductor layers respectively. The fabricated n-channel field-effect-transistor (FET) showed the low threshold voltage and leakage currents because of the stronger connection between the nanocomposite and n-type Si substrate. Whereas, dominated hydroxyl groups in the nanocomposite dielectric film deposited on the p-type Si substrate increased trap states in the interface, led to the drop of FET operation.

• 한국전기전자재료학회논문지
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• 제23권8호
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• pp.605-610
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• 2010

The devices based on electrically erasable programmable read-only memory (EEPROM) structure are proposed for the detection of external electric charges. A large size charge contact window (CCW) extended from the floating gate is employed to immobilize external charges, and a control gate with stacked metal-insulator-metal (MIM) capacitor is adapted for a standard single polysilicon CMOS process. When positive voltage is applied to the capacitor of CCW of an n-channel EEPROM, the drain current increases due to the negative shift of its threshold voltage. Also when a pre-charged external capacitor is directly connected to the floating gate metal of CCW, the positive charges of the external capacitor make the drain current increase for n-channel, whereas the negative charges cause it to decrease. For an p-channel, however, the opposite behaviors are observed by the external voltage and charges. With the attachment of external charges to the CCW of EEPROM inverter, the characteristic inverter voltage behavior shifts from the reference curve dependent on external charge polarity. Therefore, we have demonstrated that the EEPROM inverter is capable of detecting external immobilized charges on the floating gate. and these devices are applicable to sensing the pH's or biomolecular reactions.

• 한국전기전자재료학회논문지
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• 제11권12호
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• pp.1122-1127
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• 1998

Group II-AF_2$films such as $CaF_2$, $SrF_2$, and $BaF_2$ have been commonly used many practical applications such as silicon on insulatro(SOI), three-dimensional integrated circuits, buffer layers, and gate dielectrics in filed effect transistor. This paper presents electrical and structural properties of fluoride films as a gate dielectric layer. Conventional gate dielectric materials of TFTs like oxide group exhibited problems on high interface trap charge density($D_it$), and interface state incorporation with O-H bond created by mobile hydrogen and oxygen atoms. To overcome such problems in conventional gate insulators, we have investigated $CaF_2$ films on Si substrates. Fluoride films were deposited using a high vacuum evaporation method on the Si and glass substrate. $CaF_2$ films were preferentially grown in (200) plane direction at room temperature. We were able to achieve a minimum lattice mismatch of 0.74% between Si and $CaF_2$ films. Average roughness of $CaF_2$ films was decreased from 54.1 ${\AA}$ to 8.40 ${\AA}$ as temperature increased form RT and $300^{\circ}C$. Well fabricated MIM device showed breakdown electric field of 1.27 MV/cm and low leakage current of $10^{-10}$ A/$cm^2$. Interface trap charge density between $CaF_2$ film and Si substrate was as low as $1.8{\times}10^{11}cm^{-2}eV^{-1}$.

• 대한전자공학회논문지SD
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• 제38권11호
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• pp.765-770
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• 2001

고온 급속 열처리시킨 LiNbO₃/AIN/Si(100) 구조를 이용하여 MFIS 소자를 제작하고, 비휘발성 메모리 동작 가능성을 확인하였다. 고유전율 AIN 박막 위에 Pt 전극을 증착시켜 제작한 MIS 구조에서 측정한 1MHz C-V 특성곡선에서는 히스테리시스가 전혀 없고 양호한 계면특성을 보였으며, 축적 영역으로부터 산출한 비유전율 값은 약 8 이었다. Pt/LiNbO₃/AIN/Si(100) 구조에서 측정한 1MHz C-V 특성의 축적영역에서 산출한 LiNbO₃ 박막의 비유전율 값은 약 23 이었으며, ±5 V의 바이어스 범위 내에서의 메모리 윈도우는 약 1.2 V이었다. 이 MFIS 구조에서의 게이트 누설전류밀도는 ±500 kV/cm의 전계 범위 내에서 10/sup -9/ A/㎠ 범위를 유지하였다. 500 kHz의 바이폴러 펄스를 인가하면서 측정한 피로특성은 10/sup 11/ cycle 까지 초기값을 거의 유지하는 우수한 특성을 보였다.

• 한국재료학회지
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• 제16권5호
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• pp.302-307
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• 2006

The formation and processing of organic insulators on the device performance have been studied in the fabrication of organic thin film transistors (OTFTs). The series of polyvinyls, poly-4-vinyl phenol(PVP) and polyvinyltoluene (PVT), were used as solutes and propylene glycol monomethyl ether acetate(PGMEA) as a solvent in the formation of organic insulators. The cross-linking of organic insulators was also attempted by adding the thermosetting material, poly (melamine-co-formaldehyde) as a hardener in the compound. The electrical characteristics measured in the metal-insulator-metal (MIM) structures showed that insulating properties of PVP layers were generally superior to those of PVT layers. Among the layers of PVP series: PVP(10 wt%) copolymer, 5 wt% cross-linked PVP(10 wt%), PVP(20 wt%) copolymer, 5 wt% cross-linked PVP(20 wt%) and 10 wt% cross-linked PVP(20 wt%), the 10 wt% cross-linked PVP(20 wt%) layer showed the lowest leakage current characteristics. Finally, inverted staggered OTFTs using the PVP(20 wt%) copolymer, 5 wt% cross-linked PVP(20 wt%) and 10 wt% cross-linked PVP(20 wt%) as gate insulators were fabricated on the polyether sulphone (PES) substrates. In our experiments, we could obtain the maximum field effect mobility of 0.31 $cm^2/Vs$ in the device from 5 wt% cross-linked PVP(20 wt%) and the highest on/off current ratio of $1.92{\times}10^5$ in the device from 10 wt% cross-linked PVP(20 wt%).

• 반도체디스플레이기술학회지
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• 제5권1호
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• pp.39-43
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• 2006

The polyvinyl series organic films as gate insulators of thin film transistor(TFT) have been processed and characterized on the polyether sulphone (PES) substrates . The poly-4-vinyl phenol(PVP) and polyvinyl toluene (PVT) were used as solutes and propylene glycol monomethyl ether acetate(PGMEA) as a solvent in the formation of organic insulators. The cross-linking of organic insulators was also attempted by adding the thermosetting material, poly (melamine-co-formaldehyde) as a hardener in the compound. The electrical characteristics measured in the metal-insulator-metal (MIM) structures showed that insulating properties of PVP layers were generally superior to those of PVT layers. Among the layers of PVP series; copolymer PVP(10 wt%), 5wt% cross-linked PVP(10 wt%), copolymer PVP(20 wt%), 5 wt% cross-linked PVP(20 wt%) and 10 wt% cross-linked PVP(20 wt%), the 10 wt% cross-linked PVP(20 wt%) layer showed the lowest leakage current of 1.2 pA at ${\pm}10V$. The ms value of surface roughness and the capcitance per unit area are 2.41 and $1.76nF/cm^2$ in the case of 10 wt% cross-linked PVP(20 wt%) layer, respectively.