• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.88-92
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• 1990

An accurate analytical threshold model is presented for fully depleted SOI which has a Metal-Insulator-Semiconductor-Insulator-Metal structure. The threshold voltage is defined as the gate voltage at which the second derivative of the inversion charge with respect to the gate voltage is maximum. Therefore the model is self-consistent with the measurement scheme. Numerical simulations show good agreement with the model with less than 3% error.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1312-1314
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• 2007

The effect of gate insulator surface treatment on electrical characteristics of bottom contact (BC) and suspended source/drain (SSD) organic thinfilm transistors (OTFTs) was studied. Triisopropylsilylethynyl pentacene was used as an active material and was printed by ink-jet printing method. In case of the BC OTFTs, threshold voltage was shifted from positive to near zero, and the fieldeffect mobility was increased when the gate insulator surface was treated with hexamethyldisilazane. However, in case of SSD OTFT, threshold voltage shift was not observed and the field-effect mobility was decreased.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1998.06a
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• pp.145-148
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• 1998

Fluoride({{{{ { CaF}_{2 } }}}}) films exhibited a cubic structure with similar lattice constant to that of Si and have sufficient breakdown electric field as gate dielectric material. Therefore, {{{{ { CaF}_{2 } }}}} are expected to replace conventional insulator such {{{{ { SiO}_{ 2},{Ta}_{2}{O}_{ 2} and{Al}_{2}{O}_{5}. However, {CaF}_{2}}}}} films showed hystereisis properties due to mobile charges in the film. To solve this problem we performed thermal treatment and achieves field. C-v results indicate a reduced hystereisis window of {{{{ }}}}ΔV =0.2v, LOW INTERFACE STATE {{{{{D}_{it}=2.0 TIMES {10}^{11}{cm}^{-1}{eV}^{-1}}}}} in midgap, and good WIS diode properties. We observed a preferential crystallization of(200) plane from XRD analysis. RTA treatment effects on various material properties of {{{{{CaF}_{2}}}}} are presented in this paper.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1166-1169
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• 2006

In this study, the effects of SAMs on the performance of OTFTs have been investigated. ALD technique was applied for the deposition of SAMs, which is an ultra-thin film deposition technique based on sequences of self-limiting surface reactions enabling thickness control on atomic scale. According to our investigation results, it is observed that the surface properties of the gate insulator was changed by SAMs, which allow pentacene molecules to be deposited in the upright direction on the gate insulator and hence the performance of OTFTs could be improved. These results will be discussed

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1313-1316
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• 2005

In the present paper, it was investigated that adhesion layer on gate insulator could affect the electrical characteristics for the organic thin film transistors (OTFTs). The polyimide (PI) as organic adhesion layer was fabricated by using the vapor deposition polymerization (VDP) processing . It was found that electrical characteristics improved comparing OTFTs using adhesion layer to another. We researched adhesion layer as a function of thickness. For inverted-staggered top contact structure, field effect mobility, threshold voltage, and on-off current ratio of OTFTs using adhesion layer of PI 15 nm thickness on the gate insulator with a thickness of 0.2 ${\mu}m$ were about 0.5 $cm^2/Vs$, -0.8 V, and $10^6$, respectively.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1515-1517
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• 2001

In this work the electrical characteristics of organic TFTs with the semiconductor-insulator interfaces have been interested. Pentacene is used as an active semiconducting layer. The semiconductor layer of pentacene was thermally evaporated in vacuum at a pressure of about $2{\times}10^{-6}$ Torr and at a deposition rate of 0.3$\AA$/sec. Aluminium and gold were used for gate and source/drain electrodes. before pentacene is deposited on the insulator, the gate dielectric surfaces of two samples were rubbed with lateral and perpendicular to direction of the channel length respectively.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.543-544
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• 2006

Pentacene thin film transistors fabricated without photolithographic patterning were fabricated on the plastic substrates. Both the organic/inorganic thin films and metallic electrode were patterned by shifting the position of the shadow mask which accompanies the substrate throughout the deposition process. By using an optically transparent zirconium oxide ($ZrO_2$) as a gate insulator and octadecyltrimethoxysilane (OTMS) as an organic molecule for self-assembled monolayer (SAM) to increase the adhesion between the plastic substrate and gate insulator and the mobility with surface treatment, high-performance transistor with field effect mobility $.66\;cm^2$/V s and $I_{on}/I_{off}$>$10^5$ was formed on the plastic substrate. This technique will be applicable to all structure deposited at low temperature and suitable for an easy process for flexible display.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.545-548
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• 1998

Thin film SOI(Silicon-On-Insulator) devices exhibit floating body effect. In this paper, SOI NMOSFET is proposed to solve this problem. Some part of gate oxide was considered to be 30nm~80nm thicker than the other normal gate oxide and simulated with TSUPREM-4. The I-V characteristics were simulated with 2D MEDICI mesh. Since part of gate oxide has different oxide thickness in proposed device, the gate electric field strength is not the same throught the gate and consequently the reduction of current kink effect is occurred.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.18-26
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• 2004

Back-gated silicon-on-insulator MOSFET -a threshold-voltage adjustable device-employs a constant back-gate potential to terminate source-drain electric fields and to provide carrier confinement in the channel. This suppresses shortchannel effects of nano-scale and of high drain biases, while allowing a means to threshold voltage control. We report here a theoretical analysis of this geometry to identify its natural length scales, and correlate the theoretical results with experimental device measurements. We also analyze experimental electrical characteristics for misaligned back-gate geometries to evaluate the influence on transport behavior from the device electrostatics due to the structure and position of the back-gate. The backgate structure also operates as a floating-gate nonvolatile memory (NVRAM) when the back-gate is floating. We summarize experimental and theoretical results that show the nano-scale scaling advantages of this structure over the traditional front floating-gate NVRAM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.