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Theoretical and Experimental Analysis of Back-Gated SOI MOSFETs and Back-Floating NVRAMs  

Avci, Uygar (School of Applied and Engineering Physics)
Kumar, Arvind (School of Electrical and Computer Engineering Cornell University)
Tiwari, Sandip (School of Electrical and Computer Engineering Cornell University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.4, no.1, 2004 , pp. 18-26 More about this Journal
Abstract
Back-gated silicon-on-insulator MOSFET -a threshold-voltage adjustable device-employs a constant back-gate potential to terminate source-drain electric fields and to provide carrier confinement in the channel. This suppresses shortchannel effects of nano-scale and of high drain biases, while allowing a means to threshold voltage control. We report here a theoretical analysis of this geometry to identify its natural length scales, and correlate the theoretical results with experimental device measurements. We also analyze experimental electrical characteristics for misaligned back-gate geometries to evaluate the influence on transport behavior from the device electrostatics due to the structure and position of the back-gate. The backgate structure also operates as a floating-gate nonvolatile memory (NVRAM) when the back-gate is floating. We summarize experimental and theoretical results that show the nano-scale scaling advantages of this structure over the traditional front floating-gate NVRAM.
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