• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.153-154
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• 2000

Large size poly-Si TFT-LCDs have been fabricated using p-channel thin film transistors for notebook PC application. We have designed and implemented the data sampling circuit and gate drivers that operate with low power consumption and high reliability. The gate driver has a redundant structure. We have realized the uniform and excellent display quality comparable to that of CMOS module. The reliability of panel is investigated and discussed by measuring the bias stability of transistors.

• Journal of Power Electronics
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• v.15 no.4
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• pp.951-963
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• 2015

In this paper, a new symmetric multilevel inverter is proposed. A simple structure for the cascaded multilevel inverter topology is also proposed, which produces a high number of levels with the application of few power electronic devices. The symmetric multilevel inverter can generate 2n+1 levels with a reduced number of power switches. The basic unit is composed of a single and double source unit (SDS-unit). The application of this SDS-unit is for reducing the number of power electronic components like insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocked voltages by switches. Various new algorithms are recommended to determine the magnitude of dc sources in a cascaded structure. Furthermore, the proposed topology is optimized for different goals. The proposed cascaded structure is compared with other similar topologies. For verifying the performance of the proposed basic symmetric and cascaded structure, results from a computer-based MATLAB/Simulink simulation and from experimental hardware are also discussed.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1141-1144
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• 1998

A new design methodology for the shortchannel CMOS IC-package is presented. It is developed by representing the package inductance with an effective lumpedinductance. The worst case maximum-simultaneous-switching noise (SSN) and gate propagation delay due to the package are modeled in terms of driver geometry, the maximum number of simultaneous switching drivers, and the effective inductance. The SSN variations according to load capacitances are investigated with this model. The package design techniques based on the proposed guidelines are verified by performing HSPICE simulations with the $0.35\mu\textrm{m}$ CMOS model parameters.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.73-74
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• 2012

본 논문은 브릿지형 컨버터에 존재하는 기생성분이 게이트 구동에 미치는 영향을 분석한다. 다양한 기생성분과 입출력 사양에 따라 게이트 구동을 저해하는 EMI의 크기가 어떻게 변하는지 그 관계를 밝힌다. 이론적 분석을 통하여 시뮬레이션 모델을 구축하고, 실험을 통하여 타당성을 증명한다.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.456-459
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• 1999

This paper presents about EL(electroluminescent) driver with inverter. Inverter is composited two FET to increase safety output voltage. As result this study, the optimum operating condition of inverter is that the gate bias frequency of FET equal two resonant frequency of circuit. It shows to ideal sinusoidal output wave. Finally, EL sampler(15cm$\times$15cm) gain 2.6 [lux] with 1cm.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.43-44
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• 2010

본 논문에서는 저전압 구동 인버터의 게이트 구동회로 설계 시, 밀러 캡 영향이 야기할 수 있는 암 단락 현상 방지를 위한 양전원 방식의 게이트 구동회로 설계를 제안한다. 제안하는 회로는 부트스트랩 방식의 0~15[V] 의 전원을 사용하고, 커패시터와 다이오드를 통하여 마이너스 전압을 생성하며 이를 통해 양전원으로 게이트를 구동한다. 이는 단 전원 방식에 비하여 밀러 캡의 영향을 줄일수 있고 이를 통해 스위칭 시 소자의 스트레스를 감소시키며 또한 암단락을 방지한다. 제안하는 회로를 시뮬레이션과 실험을 통해 검증하였다.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.448-449
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• 2018

최근, WBG 반도체 소자에 대한 연구가 활발히 진행됨에 따라 고속 스위칭으로부터 발생되는 문제점들을 해결하기 위한 여러 방안들이 제시되고 있다. WBG 반도체 소자의 안정적인 고속 스위칭을 실현하기 위해서는 게이트 드라이버 내에 존재하는 기생 인덕턴스를 최소화하는 것이 가장 중요하다. 본 논문에서는 layout의 최적화 설계를 통해 GaN FET 구동용 게이트 드라이버 내의 기생 인덕턴스를 최소화할 수 있는 방안을 제시하고 설계를 통해 만들어진 게이트 드라이버를 실험을 통해 스위칭 특성을 분석하였다.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.226-227
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• 2016

본 논문은 SiC Mosfet Gate Driver에서 Overcurrent상황 발생시 Mosfet 양단의 전압을 검출함으로써 스위칭 소자를 보호하는 Desaturation detction circuit에 대해 다룬다. IGBT와 다르게 SiC Mosfet의 경우 ohmic 영역과 saturation영역의 구분이 명확하지 않기 때문에 과전류 발생시 Mosfet 양단 전압을 검출하는데 어려움이 있다. 따라서 이를 보완하기 위하여 Mosfet drain측에 새로운 회로를 추가로 설계함으로써 이를 보완하여 효과적으로 양단전압을 검출한다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.59-68
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• 1999

The timing characteristics of an ASIC are analyzed based on the propagation delays of each gate and interconnect wire. The gate delay can be modeled using the two-dimensional delay table whose index variables are the input transition time and the output load capacitance. The AWE technique can be adopted as an algorithm to compute the interconnect delay. Since these delays are affected by the interaction to the two-dimensional delay table and the AWE technique. A method to model this effect has been proposed through the effective capacitance and the gate driver model under the assumption of single driving gate. This paper presents a new technique to handle the multiple CMOS gates driving interconnect wire by extending previous approach. This technique has been implemented in C language and applied to several interconnect circuits driven by multiple CMOS gates. In most cases, we found a few tens of speed-up and only a few percents of errors in computing both of gate and interconnect delays, compared to SPICE.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.