• 한국세라믹학회지
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• 제23권4호
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• pp.55-61
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• 1986

Phosphosilicate glass(PSG) films have been used as fusable deposited dielectrics in silicon gate MOS integrated circuits. But in this experiment BPSG(borophosphosilicate glass) will be optimized for more efficient utilization of the reactants. The BPSG films were deposited on silicon wafers by the oxidation of the hydrides at 430$^{\circ}$C in conventional atmospheric-pressure chemical-vapor-deposition (CVD) systems. Physical and chemical properties of CVD BPSG films have been characterized both for as-deposited and for fused films The. relationship between deposited BPSG film composition and infra-red absorption solution etch rate and fusion temperature is discussed and examples of BPSG composition that can be fused at 900~95$0^{\circ}C$ and 800~85$0^{\circ}C$ are given. In addition to having lower fusion temperature than PSG films BPSG films have lower as-deposited intrinsic tensile stress and low aqueous chemical etch rate they have been considered for applications where these characteristics are advantageous.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.563-565
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• 2009

We introduce the new modification approaches of photocrosslinkable poly (4-vinylphenol) (PVP) for low hysteresis organic thin film transistors (OTFTs). The dielectric layers were composed of different PVP resin, low molecular melamine, and halogen free photo-initiator. The low hysteresis OTFT from one of the organic gate dielectrics has been realized. The electrical performance of low hysteresis OTFT with photocrosslinkable PVP exhibited a field-effect mobility of 0.2 cm2/Vs, a threshold voltage of - 0.04V, hysteresis of 0.4V.

• 한국전기전자재료학회논문지
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• 제16권9호
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• pp.771-774
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

• 반도체디스플레이기술학회지
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• 제9권3호
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• pp.75-78
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• 2010

In this study we investigated the electrical properties of ZnO-based MOS capacitor with $HfO_2$ as the gate dielectric. MIM capacitor, which uses either $HfO_2$ or $Al_2O_3$ as the dielectric layer, is also studied to understand the dependency of the dielectrics on the preparation conditions. It was found that thinner $HfO_2$ films yield better electrical properties, namely lower leakage current and higher breakdown electric field. These properties were observed to deteriorate when subsequently annealed. Capacitance in the depletion region of MOS capacitor was found to increase with UV ozone treatment time up to 60min. However, when the treatment time was extended to 120min, the trend is reversed. The 'threshold voltage' was also observed to positively shift with UV ozone treatment time up to 60min. The shift apparently saturated for longer treatment.

• 접착 및 계면
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• 제22권3호
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• pp.91-97
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• 2021

본 연구는 Parylene C 유전체 표면에 유기 자기조립단분자막(self-assembled monolayer, SAM) 중간층을 도입함으로써 표면특성을 제어하고 최종적으로 유기전계효과 트랜지스터(organic field-effect transistors, OFETs)의 전기적 안정성을 향상시킨 결과를 제시하였다. 유기 중간층을 적용함으로써, Parylene C 게이트 유전체의 표면 에너지를 제어하였으며, OFET의 가장 중요한 성능변수인 전계효과 이동도(field-effect transistor, μ_FET)와 문턱 전압 (threshold voltage, V_th)의 성능향상과 구동 안정성을 증대시켰다. 단순히 Parylene C 유전체를 적용한 Bare OFET에서 μ_FET 값은 0.12 cm²V^-1s^-1가 측정되었으나, hexamethyldisilazane (HMDS)과 octadecyltrichlorosilane (ODTS)를 중간층으로 적용된 소자에서는 각각 0.32과 0.34 cm²V^-1s^-1로 μ_FET가 증가하였다. 또한 1000번의 transfer 특성의 반복측정을 통해 ODTS 처리한 OFET의 μ_FET와 V_th의 변화가 가장 작게 나타남을 확인하였다. 이 연구를 통해 유기 SAM 중간층, 특히 ODTS는 효과적으로 Parylene C 표면을 알킬 사슬로 덮어 극성도를 낮춤과 함께 전하 트래핑을 감소시켜 소자의 전기적 구동 안정성을 증가시킬 수 있음을 확인하였다.

• 한국정보통신학회논문지
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• 제18권1호
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• pp.135-141
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• 2014

본 연구에서는 무접합 MuGFET의 핀 폭에 따른 문턱전압의 변화를 줄이기 위한 소자 설계 가이드라인을 제시하였다. 제작된 무접합 MuGFET으로부터 핀 폭이 증가할수록 문턱전압의 변화가 증가하는 것을 알 수 있었다. 무접합 MuGFET의 핀 폭에 따른 문턱전압의 변화를 줄이기 위한 소자 설계가이드라인으로 게이트 유전체, 실리콘박막의 두께, 핀 수를 최적화 하는 연구를 3차원 소자 시뮬레이션을 통해 수행하였다. 고 유전율을 갖는 $La_2O_3$ 유전체를 게이트 절연층으로 사용하거나 실리콘 박막을 최대한 얇게 하므로 핀 폭이 증가해도 문턱전압의 변화율을 줄일 수 있음을 알 수 있었다. 특히 유효 채널 폭을 같게 하면서 핀 수를 많게 하므로 문턱전압 변화율과 문턱전압 아래 기울기를 작게 하는 것이 무접합 MuGFET의 최적의 소자 설계 가이드라인임을 알 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.237.1-237.1
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• 2016

Electrical properties of graphene-based field effect transistors (G-FETs) can be degraded in ambient conditions owing to physisorbed oxygen or water molecules on the graphene surface. Passivation technique is one of a fascinating strategy for fabrication of G-FETs, which allows to sustain electrical properties of graphene in the long term without disrupting its inherent properties: transparency, flexibility and thinness. Ironically, despite its importance in producing high performance graphene devices, this method has been much less studied compared to patterning or device fabrication processes. Here we report a novel surface passivation method by using atomically thin self-assembled alkane layers such as C18- NH2, C18-Br and C36 to prevent unintentional doping effects that can suppress the degradation of electrical properties. In each passivated device, we observe a shift in charge neutral point to near zero gate voltage and it maintains the device performance for 1 year. In addition, the fabricated PG-FETs on a plastic substrate with ion-gel gate dielectrics exhibit not only mechanical flexibility but also long-term stability in ambient conditions. Therefore, we believe that these highly transparent and ultra-thin passivation layers can become a promising candidate in a wide range of graphene based electronic applications.

• 마이크로전자및패키징학회지
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• 제11권2호
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• pp.29-35
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• 2004

65 nm급 게이트 유전체로의 $HfO_2$의 적용을 위해 hydrogen-terminate된 Si 기판과 ECR $N_2$ plasma를 이용하여 SiNx를 형성한 기판 위에 MOCVD를 이용하여 $HfO_2$를 증착하였다. $450^{\circ}C$에서 증착시킨 박막의 경우 낮은 carbon 불순물을 가지며 비정질 matrix에 국부적인 결정화와 가장 적은 계면층이 형성되었으며 이 계면층은 Hf-silicate임을 알 수 있었다. 또한 $900^{\circ}C$, 30초간 $N_2$분위기에서 RTA 결과 $HfO_2/Si$의 single layer capacitor의 경우 계면층의 증가로 인해 EOT가 열처리전(2.6nm)보다 약 1 nm 증가하였다. 그러나 $HfO_2/SiNx/Si$ stack capacitor의 경우 SiNx 계면층은 열처리후에도 일정하게 유지되었으며 $HfO_2$ 박막의 결정화로 열처리전(2.7nm)보다 0.3nm의 EOT 감소를 나타내었으며 열처리후에도 $4.8{\times}10^{-6}A/cm^2$의 매우 우수한 누설전류 특성을 가짐을 알 수 있었다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.620-621
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• 2008

Transparent electronics has been one of the key terminologies forecasting the ubiquitous technology era. Several researchers have thus extensively developed transparent oxide-based thin-film transistors (TFTs) on glass and plastic substrates although in general high voltage operating devices have been mainly studied considering transparent display drivers. However, low voltage operating oxide TFTs with transparent electrodes are very necessary if we are aiming at logic circuit applications, for which transparent complementary or one-type channel inverters are required. The most effective and low power consuming inverter should be a form of complementary p-channel and n-channel transistors but real application of those complementary TFT inverters also requires electrical- and even photo-stabilities. Since p-type oxide TFTs have not been developed yet, we previously adopted organic pentacene TFTs for the p-channel while ZnO TFTs were chosen for n-channel on sputter-deposited $AlO_x$ film. As a result, decent inverting behavior was achieved but some electrical gate instability was unavoidable at the ZnO/$AlO_x$ channel interface. Here, considering such gate instability issues we have designed a unique transparent complementary TFT (CTFTs) inverter structure with top n-ZnO channel and bottom p-pentacene channel based on 12 nm-thin nano-oxide/self assembled monolayer laminated dielectric, which has a large dielectric strength comparable to that of thin film amorphous $Al_2O_3$. Our transparent CTFT inverter well operate under 3 V, demonstrating a maximum voltage gain of ~20, good electrical and even photoelectric stabilities. The device transmittance was over 60 % and this type of transparent inverter has never been reported, to the best of our limited knowledge.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1993년도 춘계학술대회 논문집
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• pp.39-43
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• 1993

Electricial characteristics of gate dielectrics prepared by reoxidation of thermal $SiO_2$ in nitrous oxide gas have been investigated. 10 and 19nm-thick oxides were reoxidized at temperatures of $900-1000^{\circ}C$ for 10-60 min in $N_2O$ ambient. As reoxidation proceeds, it is shown that nitrogen concentration at $Si/SiO_2$ interface increases gradually through the AES analysis. Nitrogen pile-up at $Si/SiO_2$ interface acts as a oxidant diffusion barrier that reduces the oxidation rate significantly. And it not only strengthen oxynitride structure at the interface but improve the gate dielectric qualities. Reliabilities of oxynitride films are conformed by the breakdown distributions and constant current stress technique. Therefore, the oxynitride films made by this process show a good promise for future ULSI applications.