• Title/Summary/Keyword: Gate Dielectrics

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Progress of High-k Dielectrics Applicable to SONOS-Type Nonvolatile Semiconductor Memories

  • Tang, Zhenjie;Liu, Zhiguo;Zhu, Xinhua
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.4
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    • pp.155-165
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    • 2010
  • As a promising candidate to replace the conventional floating gate flash memories, polysilicon-oxide-nitride-oxidesilicon (SONOS)-type nonvolatile semiconductor memories have been investigated widely in the past several years. SONOS-type memories have some advantages over the conventional floating gate flash memories, such as lower operating voltage, excellent endurance and compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology. However, their operating speed and date retention characteristics are still the bottlenecks to limit the applications of SONOS-type memories. Recently, various approaches have been used to make a trade-off between the operating speed and the date retention characteristics. Application of high-k dielectrics to SONOS-type memories is a predominant route. This article provides the state-of-the-art research progress of high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories. It begins with a short description of working mechanism of SONOS-type memories, and then deals with the materials' requirements of high-k dielectrics used for SONOS-type memories. In the following section, the microstructures of high-k dielectrics used as tunneling layers, charge trapping layers and blocking layers in SONOS-type memories, and their impacts on the memory behaviors are critically reviewed. The improvement of the memory characteristics by using multilayered structures, including multilayered tunneling layer or multilayered charge trapping layer are also discussed. Finally, this review is concluded with our perspectives towards the future researches on the high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories.

Low-Voltage Operating N-type Organic Field-Effect Transistors by Charge Injection Engineering of Polymer Semiconductors and Bi-Layered Gate Dielectrics (N형 고분자 반도체의 전하주입 특성 향상을 통한 저전압 유기전계효과트랜지스터 특성 연구)

  • Moon, Ji-Hoon;Baeg, Kang-Jun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.30 no.10
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    • pp.665-671
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    • 2017
  • Herein, we report the fabrication of low-voltage N-type organic field-effect transistors by using high capacitance fluorinated polymer gate dielectrics such as P(VDF-TrFE), P(VDF-TrFE-CTFE), and P(VDF-TrFE-CFE). Electron-withdrawing functional groups in PVDF-based polymers typically cause the depletion of negative charge carriers and a high contact resistance in N-channel organic semiconductors. Therefore, we incorporated intermediate layers of a low-k polymerto prevent the formation of a direct interface between PVDF-based gate insulators and the semiconducting active layer. Consequently, electron depletion is inhibited, and the high charge resistance between the semiconductor and source/drain electrodes is remarkably improved by the in corporation of solution-processed charge injection layers.

Optimization of Gate Stack MOSFETs with Quantization Effects

  • Mangla, Tina;Sehgal, Amit;Saxena, Manoj;Haldar, Subhasis;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.3
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    • pp.228-239
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    • 2004
  • In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.

The plasma polymerized polymer thin films for application to organic thin film transistor (유기박막 트랜지스터로의 응용을 위한 플라즈마 중합 고분자 박막)

  • Lim, Jae-Sung;Shin, Paik-Kyun;Lee, Boong-Joo;You, Do-Hyun;Park, Se-Geun;Lee, El-Hang
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.1353_1354
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    • 2009
  • The OTFT devices had inverted staggered structures of Au/pentacene/ppMMA/ITO on PET substrate. The overall device performances of the flexible devices such as the operating voltage, the field effect mobility, the on/off ratio and the off current are somewhat worse than those of devices fabricated on glass substrates. Pentacene/ppMMA OTFT benchmarks (mobility, sub-threshold slope, on/off ratio) were comparable to that of solution cast PMMA, but below average when compared to other polymer gate dielectrics. However, threshold and drive voltages were among the lowest reported for a polymer gate dielectric, and surpassed only by ultra-thin SAM gate dielectrics.

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Effect of the Hydrophobicity of Hybrid Gate Dielectrics on a ZnO Thin Film Transistor

  • Choi, Woon-Seop;Kim, Se-Hyun
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.6
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    • pp.257-260
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    • 2010
  • Zinc oxide (ZnO) bottom-contact thin-film transistors (TFTs) were prepared by the use of injector type atomic layer deposition. Two hybrid gate oxide systems of different polarity polymers with silicon oxide were examined with the aim of improving the properties of the transistors. The mobility and threshold voltage of a ZnO TFT with a poly(4-dimethylsilyl styrene) (Si-PS)/silicon oxide hybrid gate dielectric had values of 0.41 $cm^2/Vs$ and 24.4 V, and for polyimide/silicon oxide these values were 0.41 $cm^2/Vs$ and 24.4 V, respectively. The good hysteresis property was obtained with the dielectric of hydrophobicity. The solid output saturation behavior of ZnO TFTs was demonstrated with a $10^6$ on-off ratio.

High-Performance Flexible Graphene Field Effect Transistors with Ion Gel Gate Dielectrics

  • Jo, Jeong-Ho
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2012.05a
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    • pp.69.3-69.3
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    • 2012
  • A high-performance low-voltage graphene field-effect transistor (FED array was fabricated on a flexible polymer substrate using solution-processable, high-capacitance ion gel gate dielectrics. The high capacitance of the ion gel, which originated from the formation of an electric double layer under the application of a gate voltage, yielded a high on-current and low voltage operation below 3 V. The graphene FETs fabricated on the plastic substrates showed a hole and electron mobility of 203 and 91 $cm^2/Vs$, respectively, at a drain bias of - I V. Moreover, ion gel gated graphene FETs on the plastic substrates exhibited remarkably good mechanical flexibility. This method represents a significant step in the application of graphene to flexible and stretchable electronics.

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Low-voltage Pentacene Field-Effect Transistors Based on P(S-r-BCB-r-MMA) Gate Dielectrics (P(S-r-BCB-r-MMA) 게이트 절연체를 이용한 저전압 구동용 펜타센 유기박막트랜지스터)

  • Koo, Song Hee;Russell, Thomas P.;Hawker, Craig J.;Ryu, Du Yeol;Lee, Hwa Sung;Cho, Jeong Ho
    • Applied Chemistry for Engineering
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    • v.22 no.5
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    • pp.551-554
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    • 2011
  • One of the key issues in the research of organic field-effect transistors (OFETs) is the low-voltage operation. To address this issue, we synthesized poly(styrene-r-benzocyclobutene-r-methyl methacrylate) (P(S-r-BCB-r-MMA)) as a thermally cross-linkable gate dielectrics. The P(S-r-BCB-r-MMA) showed high quality dielectric properties due to the negligible volume change during the cross-linking. The pentacene FETs based on the 34 nm-thick P(S-r-BCB-r-MMA) gate dielectrics operate below 5 V. The P(S-r-BCB-r-MMA) gate dielectrics yielded high device performance, i.e. a field-effect mobility of $0.25cm^2/Vs$, a threshold voltage of -2 V, an sub-threshold slope of 400 mV/decade, and an on/off current ratio of ${\sim}10^5$. The thermally cross-linkable P(S-r-BCB-r-MMA) will provide an attractive candidate for solution-processable gate dielectrics for low-voltage OFETs.

Structural and electrical characterizations of $HfO_{2}/HfSi_{x}O_{y}$ as alternative gate dielectrics in MOS devices (MOS 소자의 대체 게이트 산화막으로써 $HfO_{2}/HfSi_{x}O_{y}$ 의 구조 및 전기적 특성 분석)

  • 강혁수;노용한
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.45-49
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    • 2001
  • We have investigated physical and electrical properties of the Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin film for alternative gate dielectrics in the metal-oxide-semiconductor device. The oxidation of Hf deposited directly on the Si substrate results in the H $f_{x}$/ $O_{y}$ interfacial layer and the high-k Hf $O_2$film simultaneously. Interestingly, the post-oxidation N2 annealing of the H102/H1Si70y thin films reduces(increases) the thickness of an amorphous HfS $i_{x}$/ $O_{y}$ layer(Hf $O_2$ layer). This phenomenon causes the increase of the effective dielectric constant, while maintaining the excellent interfacial properties. The hysteresis window in C-V curves and the midgap interface state density( $D_{itm}$) of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin films less than 10 mV and ~3$\times$10$^{11}$ c $m^{-2}$ -eV without post-metallization annealing, respectively. The leakage current was also low (1$\times$10-s A/c $m^2$ at $V_{g}$ = +2 V). It is believed that these excellent results were obtained due to existence of the amorphous HfS $i_{x}$/ $O_{y}$ buffer layer. We also investigated the charge trapping characteristics using Fowler-Nordheim electron injection: We found that the degradation of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ gate oxides is more severe when electrons were injected from the gate electrode.e electrode.e.e electrode.e.

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Thermal Stability and Electrical Properties of $HfO_xN_y$ ($HfO_2$) Gate Dielectrics with TaN Gate Electrode (TaN 게이트 전극을 가진 $HfO_xN_y$ ($HfO_2$) 게이트 산화막의 열적 안정성)

  • Kim, Jeon-Ho;Choi, Kyu-Jeong;Yoon, Soon-Gil;Lee, Won-Jae;Kim, Jin-Dong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07a
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    • pp.54-57
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    • 2003
  • [ $HfO_xN_y$ ] films using a hafnium tertiary-butoxide $(Hf[OC(CH_3)_3]_4)$ in plasma and $N_2$ ambient were prepared to improve the thermal stability of hafnium-based gate dielectrics. A 10% nitrogen incorporation into $HfO_2$ films showed a smooth surface morphology and a crystallization temperature as high as $200^{\circ}C$ compared with pure $HfO_2$ films. The $TaN/HfO_xN_y/Si$ capacitors showed a stable capacitance-voltage characteristics even at post-metal annealing temperature of $1000^{\circ}C$ in $N_2$ ambient and a constant value of 1.6 nm EOT (equivalent oxide thickness) irrespective of an increase of PDA and PMA temperature. Leakage current densities of $HfO_xN_y$ capacitors annealed at PDA temperature of 800 and $900^{\circ}C$, respectively were approximately one order of magnitude lower than that of $HfO_2$ capacitors.

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