• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1046-1048
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• 2004

Performances of organic thin film transistors (OTFTs) can be detrimentally affected by the state of the gate dielectric. Because of the bad stability of polymers, OTFTs with polymer gate dielectrics often provide abnormal characteristics. In this study, we report the condensation effect of the polymer gate dielectric layer. For the observations of the effect of the condensation, the spin-coated polymer layers with various deposition conditions were fabricated and left under low vacuum condition for several days. It is observed that the thickness of polymer layer and the electrical characteristic of OTFTs vary with the condensation time.

• Journal of IKEEE
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• v.25 no.3
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• pp.501-505
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• 2021

In this study, we fabricated amorphous indium-tin-gallium-zinc-oxide thin-film transistors (a-ITGZO TFTs) with gate dielectrics of HfO₂ and the mixed layers of HfO₂ and Al₂O₃, and investigated the effect of gate dielectric on electrical characteristics of a-ITGZO TFTs. When only HfO₂ was used as the gate dielectric, the mobility and subthreshold swing (SS) were 32.3 cm²/Vs and 206 mV/dec. For the a-ITGZO TFTs with gate dielectric made of HfO₂ and Al₂O (2:1, 1:1), the mobilities and SS were 26.4 cm²/Vs (2:1), 16.8 cm²/Vs(1:1), 160 mV/dec (2:1) and 173 mV/dec (1:1). On the other hand, the hysteresis window shown in transfer curves of the a-ITGZO TFTs was lessened from 0.60 to 0.09 V by the increase of Al₂O₃ ratio in gate dielectric, indicating that the interface trap density between the gate dielectric and channel layer decreases due to Al₂O₃.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.56-56
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• 2008

ZnO Oxide TFT with organic dielectric was prepared. ZnO thin film as active channel was prepared by plasma enhanced atomic deposition technique. Organic dielectric was spin coated on the gate metal. The structure of prepared TFT is bottom gate type and top contact structure. The characterization of oxide TFT was performed. We obtained the mobility of $0.7cm^2$/Vs, the threshold voltage of -14V, and the on-off ratio of $10^4$. We also obtained good output characterization with solid saturation.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1051-1054
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• 2009

This paper investigates approaches for improving effective mobility of organic thin film transistors (OTFTs). We consider gate dielectric optimization, whereby we demonstrated >2x increase in mobility by using a silicon-rich silicon nitride ($SiN_x$) gate dielectric for polythiophene-based (PQT) OTFTs. We also engineer the dielectric-semiconductor ($SiN_x$-PQT) interface to attain a 27x increase in mobility (up to 0.22 $cm^2$/V-s) using an optimized combination of oxygen plasma and OTS SAM treatments. Augmentative material systems by combining 1-D nanomaterials (e.g., carbon nanotubes, zinc oxide nanowires) in an organic matrix for nanocomposite OTFTs provided a further boost in device performance.

• Bulletin of the Korean Chemical Society
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• v.33 no.7
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• pp.2127-2128
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• 2012

• Proceedings of the Korean Ceranic Society Conference
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• 2000.10a
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• pp.160.1-160
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• 2000

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.228-239
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• 2004

In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.8
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• pp.609-615
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• 2011

This paper is studied for the improvement of the characteristics of gate oxide with 3-nm-thick gate oxide by deuterium ion implantation methode. Deuterium ions were implanted to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas to nitrogen was performed to remove the damage of D-implantation. We simulated the deuterium ion implantation to find the optimum condition by SRIM (stopping and range of ions in matter) tool. We got the optimum condition by the results of simulation. We compare the electrical characteristics of the optimum condition with others terms. We also analyzed the electrical characteristics to change the annealing conditions after deuterium ion implantation. The results of the analysis, the breakdown time of the gate oxide was prolonged in the optimum condition. And a variety of annealing, we realized the dielectric property that annealing is good at longer time. However, the high temperature is bad because of thermal stress.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.252-255
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• 2013

Nano MOS with $Er_2O_3/SiO_2$ double-layer gate dielectrics was demonstrated by EDISON Nanophysics software. Double-layer structure decreases the gate leakage current in two orders compared with $SiO_2$ single-layer gate dielectric.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2070-2078
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• 2014

In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage transfer curves (VTCs) of a common-source (CS) amplifier based on the HGD pnpn TFET, the operation point (Q-point) was obtained at $V_{DS}=1V$, where the maximum available output swing was acquired without waveform distortion. The slope of VTC of the amplifier was 9.21 V/V (19.4 dB), which mainly resulted from the ponderable direct-current (DC) characteristics of HGD pnpn TFET. Along with the DC performances, frequency response with a small-signal voltage of 10 mV has been closely investigated in terms of voltage gain ($A_v$), unit-gain frequency ($f_{unity}$), and cut-off frequency ($f_T$). The Ge/GaAs HGD pnpn TFET demonstrated $A_v=19.4dB$, $f_{unity}=10THz$, $f_T=0.487$ THz and $f_{max}=18THz$.