• Korean Journal of Materials Research
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• v.15 no.2
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• pp.139-142
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• 2005

[ $ZrO_2$ ] gate dielectric thin films were deposited by radio frequency (rf)-magnetron sputtering and its structure, surface morphology and electrical peoperties were studied. As the oxygen flow rate increases, the surface becomes smoother. The experimental results indicate that a high temperature annealing is desirable since it improves the electrical properties of the $ZrO_2$ gate dielectric thin films by decreasing the number of interfacial traps at the $ZrO_2/Si$ interface. The carrier transport mechanism is dominated by the thermionic emission.

• Transactions on Electrical and Electronic Materials
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• v.11 no.6
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• pp.257-260
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• 2010

Zinc oxide (ZnO) bottom-contact thin-film transistors (TFTs) were prepared by the use of injector type atomic layer deposition. Two hybrid gate oxide systems of different polarity polymers with silicon oxide were examined with the aim of improving the properties of the transistors. The mobility and threshold voltage of a ZnO TFT with a poly(4-dimethylsilyl styrene) (Si-PS)/silicon oxide hybrid gate dielectric had values of 0.41 $cm^2/Vs$ and 24.4 V, and for polyimide/silicon oxide these values were 0.41 $cm^2/Vs$ and 24.4 V, respectively. The good hysteresis property was obtained with the dielectric of hydrophobicity. The solid output saturation behavior of ZnO TFTs was demonstrated with a $10^6$ on-off ratio.

• Journal of Korea Society of Industrial Information Systems
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• v.17 no.3
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• pp.27-34
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• 2012

This paper presents the impact of time dependent dielectric breakdown (TDDB, also called as gate oxide breakdown) failure on nanoscale digital CMOS Circuits. Recently, TDDB for ultra-thin gate oxides has been considered as one of the critical reliability issues which can lead to performance degradation or logic failures in nanoscale CMOS devices. Also, leakage power in the standby mode can be increased significantly. In this paper, TDDB aging effects on large CMOS digital circuits in the 45nm technology are analyzed. Simulation results show that TDDB effect on MOSFET circuits can result in more significant increase of power consumption compared to delay increase.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.551-555
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• 2013

Linearity characteristics of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) have been compared with those of high-k-only and $SiO_2$-only TFETs in terms of IIP3 and P1dB. It has been observed that the optimized HG TFETs have higher IIP3 and P1dB than high-k-only and $SiO_2$-only TFETs. It is because HG TFETs show higher transconductance ($g_m$) and current drivability than $SiO_2$-only TFETs and $g_m$ less sensitive to gate voltage than high-k-only TFETs.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.972-973
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• 2007

Relationships between field effect mobility and grain size on pentacene thin-film transistors with $polyimide/SiO_2$ gate dielectrics have been studied. 6 kinds of polyimide were used as surface treatment gate dielectric layer. Grain size of the pentacene thin film were between 5 and $30\;{\mu}m$ and depended on the polyimide. The field effect mobility were also depended on the polyimide and the those values were from 0.027 to $0.69\;cm^2/(Vs)$. The field effect mobility tends to increase with increasing the grain size. Precursor type polyimide containing polyamic acid show better mobility of $0.69\;cm^2/(Vs)$ than soluble type polyimide. Bias stress characteristics in air are discussed in the basis of the grain size.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.44-48
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• 1999

In order to the investigate for the DC(forward-reverse) breakdown properties of gate oxide in MOSFET, we are manufactured the specimen as following. The resistivity is 1.2($\Omega$ $.$ cm), 1.5($\Omega$ $.$ cm) and 1.8($\Omega$ $.$ cm) when thickness is 600(${\AA}$), and the diffusion time is both 110[min] and 150[min] when thickness is 600[${\AA}$]. In DC dielectric strength due to the each resistivity, it is confirmed that almost of the leakage current and breakdown current is flowed through n+ source when positive bias is applied, but is flowed through P region when negative bias is applied. It is thought that the dielectric strength due to the diffusion time is the contribution as increasing of p region.

• Journal of Sensor Science and Technology
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• v.28 no.1
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• pp.17-22
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• 2019

As CMOS technology scales down, reliability is becoming an important concern for VLSI designers. This paper analyzes gate-oxide breakdowns (i.e., the time-dependent dielectric-breakdown (TDDB) aging effect) as a reliability issue for combinational circuits with 45-nm technology. This paper shows simulation results for the noise margin, delay, and power using a single inverter-chain circuit, as well as the International Symposium on Circuits and Systems (ISCAS)'85 benchmark circuits. The delay and power variations in the presence of TDDB are also discussed in the paper. Finally, we propose a novel method to compensate for the logic failure due to dielectric breakdowns: We used a higher supply voltage and a negative ground voltage for the circuit. The proposed method was verified using the ISCAS'85 benchmark circuits.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.465-465
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• 2013

Inorganic 물질인 SiO2 dielectric 위에 organic dielectric PVP (4-vinyphenol)를 spin coating으로 올려, inorganic/organic dielectric 형태의 double layer구조로 High-performance amorphous indiumgallium zinc oxide thin-film transistors (IGZO TFT)를 제작하여 보았다. SiO2 dielectric을 buffer layer로 80 nm, PVP는 10Wt% 400 nm로 구성하였으며, 200 nm single SiO2 dielectric과 동일한 수준의 leakage current 특성을 MIM Capacitor 구조를 통해서 확인할 수 있었다. 이 소자의 장점은 용액공정의 도입으로 공정 시간의 단축 및 원가 절감을 이룰 수 있으며, dielectric과 channel 사이의 균일한 interface의 형성으로 interface trap 개선 및 Yield 향상의 장점을 갖는다. 우리는 실험을 통해서 SiO2 buffer layer가 수직 electric field에 의한 leakage current을 제어하고, PVP dielectric은 interface를 개선하는 것을 확인하였다. Vth의 negative shift 및 slope의 향상으로 구동전압이 줄어들고, 균일한 I-V Curve 형성을 통해서 Process Yield의 향상을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05a
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• pp.86-89
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• 2004

Organic thin film transistors (OTFTs) are fabricated on the plastic substrate through 4-level mask process without photolithographic patterning to yield the simple fabrication process. And we herewith report for the effect of dielectric surface modification on the electrical characteristics of OTFTs. The KIST-JM-1 as an organic molecule for the surface modification is deposited onto the surface of zirconium oxide $(ZrO_2)$ gate dielectric layer. In this work, we have examined the dependence of electrical performance on the interface surface state of gate dielectric/pentacene, which may be modified by chemical properties in the gate dielectric surface.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.20-23
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• 2000

We have investigated a process for the preparation of high-quality tantalum oxynitride ( $T_{a}$ $O_{x}$ $N_{y}$) via the N $H_3$ annealing of 7$_{a2}$ $O_{5}$, for use in gate dielectric applications. Compared with tantalum oxide (7$_{a2}$ $O_{5}$), a significant improvement in the dielectric constant was obtained by the N $H_3$ treatment. In addition, light reoxidation in a wet ambient at 45$0^{\circ}C$ resulted in a significantly reduced leakage current. We confirmed nitrogen incorporation in the tantalum oxynitride ( $T_{a}$ $O_{x}$ $N_{y}$ by Auger Electron Spectroscopy. By optimizing the nitridation and reoxidation process, we obtained an equivalent oxide thickness as thin as 1.6nm and a leakage current of less than 10mA/$\textrm{cm}^2$ at 1.5V..5V..5V..5V..5V..5V.