• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.1046-1048
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• 2004

Performances of organic thin film transistors (OTFTs) can be detrimentally affected by the state of the gate dielectric. Because of the bad stability of polymers, OTFTs with polymer gate dielectrics often provide abnormal characteristics. In this study, we report the condensation effect of the polymer gate dielectric layer. For the observations of the effect of the condensation, the spin-coated polymer layers with various deposition conditions were fabricated and left under low vacuum condition for several days. It is observed that the thickness of polymer layer and the electrical characteristic of OTFTs vary with the condensation time.

• 전기전자학회논문지
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• 제25권3호
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• pp.501-505
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• 2021

본 연구에서는 HfO₂와 Al₂O₃ 비율을 조절하여 게이트 절연막을 구성하고, 게이트 절연막에 따른 a-ITGZO 박막트랜지스터의 전기적 특성을 분석하였다. HfO₂ 게이트 절연막, HfO₂와 Al₂O₃ 비율이 2:1인 게이트 절연막, HfO₂와 Al₂O₃ 비율이 1:1인 게이트 절연막으로 구성된 a-ITGZO 박막트랜지스터의 전자이동도는 각각 32.3, 26.4, 16.8 cm²/Vs이고 SS 값은 각각 206, 160, 173 mV/dec 이며 히스테리시스 윈도우 폭은 각각 0.60, 0.12, 0.09 V 이었다. 게이트 절연막에서 Al₂O₃ 비율이 높아질수록 a-ITGZO 박막트랜지스터의 히스테리시스 윈도우 폭이 감소했는데, 이는 Al₂O₃ 비율이 높아질수록 게이트 절연막과 채널 박막 사이의 interface trap density가 감소했기 때문이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.56-56
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• 2008

ZnO Oxide TFT with organic dielectric was prepared. ZnO thin film as active channel was prepared by plasma enhanced atomic deposition technique. Organic dielectric was spin coated on the gate metal. The structure of prepared TFT is bottom gate type and top contact structure. The characterization of oxide TFT was performed. We obtained the mobility of $0.7cm^2$/Vs, the threshold voltage of -14V, and the on-off ratio of $10^4$. We also obtained good output characterization with solid saturation.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1051-1054
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• 2009

This paper investigates approaches for improving effective mobility of organic thin film transistors (OTFTs). We consider gate dielectric optimization, whereby we demonstrated >2x increase in mobility by using a silicon-rich silicon nitride ($SiN_x$) gate dielectric for polythiophene-based (PQT) OTFTs. We also engineer the dielectric-semiconductor ($SiN_x$-PQT) interface to attain a 27x increase in mobility (up to 0.22 $cm^2$/V-s) using an optimized combination of oxygen plasma and OTS SAM treatments. Augmentative material systems by combining 1-D nanomaterials (e.g., carbon nanotubes, zinc oxide nanowires) in an organic matrix for nanocomposite OTFTs provided a further boost in device performance.

• Bulletin of the Korean Chemical Society
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• 제33권7호
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• pp.2127-2128
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• 2012

• 한국세라믹학회:학술대회논문집
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• 한국세라믹학회 2000년도 추계총회,초청강연,특별강연,연구발표회
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• pp.160.1-160
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• 2000

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.228-239
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• 2004

In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.

• 한국전기전자재료학회논문지
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• 제24권8호
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• pp.609-615
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• 2011

This paper is studied for the improvement of the characteristics of gate oxide with 3-nm-thick gate oxide by deuterium ion implantation methode. Deuterium ions were implanted to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas to nitrogen was performed to remove the damage of D-implantation. We simulated the deuterium ion implantation to find the optimum condition by SRIM (stopping and range of ions in matter) tool. We got the optimum condition by the results of simulation. We compare the electrical characteristics of the optimum condition with others terms. We also analyzed the electrical characteristics to change the annealing conditions after deuterium ion implantation. The results of the analysis, the breakdown time of the gate oxide was prolonged in the optimum condition. And a variety of annealing, we realized the dielectric property that annealing is good at longer time. However, the high temperature is bad because of thermal stress.

• EDISON SW 활용 경진대회 논문집
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• 제2회(2013년)
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• pp.252-255
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• 2013

Nano MOS with $Er_2O_3/SiO_2$ double-layer gate dielectrics was demonstrated by EDISON Nanophysics software. Double-layer structure decreases the gate leakage current in two orders compared with $SiO_2$ single-layer gate dielectric.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2070-2078
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• 2014

In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage transfer curves (VTCs) of a common-source (CS) amplifier based on the HGD pnpn TFET, the operation point (Q-point) was obtained at $V_{DS}=1V$, where the maximum available output swing was acquired without waveform distortion. The slope of VTC of the amplifier was 9.21 V/V (19.4 dB), which mainly resulted from the ponderable direct-current (DC) characteristics of HGD pnpn TFET. Along with the DC performances, frequency response with a small-signal voltage of 10 mV has been closely investigated in terms of voltage gain ($A_v$), unit-gain frequency ($f_{unity}$), and cut-off frequency ($f_T$). The Ge/GaAs HGD pnpn TFET demonstrated $A_v=19.4dB$, $f_{unity}=10THz$, $f_T=0.487$ THz and $f_{max}=18THz$.