• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.1724-1727
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• 2005

Injection molding process is one of the processes that can mold plastic product as low cost. However, manufacturing process of automobile bumper mold has lots of trial and error. Especially, desiging of a huge mold such as bumper mold is needed to establish a design standard for runner system. In this study, CAE was conducted to observe the variation of melt-flow by changing runner and gate type in automobile bumper mold as preceding study for a standard design of runner system.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.10a
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• pp.330-335
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• 2001

Characteristics of the present world market include demanding and sophisticated customers, requirement of high quality and innovative products, greater product diversity, increasing labour and products costs, availability of diverse alternatives to the customers and smaller batch sizes to satisfy a variety of customer profiles. To fulfil these characteristics, manufacturing companies need to be flexible adaptable, proactive and able to produce variety of products in short time at low cost. The aim of the study is to develop a computer-aided design system for water-gate on AutoCAD R2000 system. The developed system has been written in AutoCAD and VisualLISP with a personal computer, and is composed four modules which are the gate-lifter input module, guide-frame input module, and upgrade module. Based on knowledge-based rules, the system is designed by considering several factors, such as width and height of a water-gate, material, object of product and maximum depth of water.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.859-862
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• 2003

This paper proposes an emulation environment for SoC designs using small number of large gate-count FPGA's and a PC system. To overcome the pin limitation problem in partitioning the design when the design size overwhelms the FPGA gate count, we use bus splitter modules that replicate on-chip bus signals in one FPGA to arbitrary number of other FPGA's with minimal pin count. The proposed scheme is applied to the emulation of 2 million gate multimedia processing chip using two Xilinx Viretex-2 6000 FPGA devices in 6.6MHz operating frequency. An ARM core, memories, camera and LCD display are modeled in software using dual 2GHz Pentium-III processors. This scheme can be utilized for more than 2 FPGA's in the same ways as two FPGA case without losing emulation speed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.85-93
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• 1984

In the paper, a new constructive initial placement algorithm is proposed in computer aided layout design in LSI. An useful object function are proposed to place the modules in logic design diagram laid down by manual to the fixed chip, reflecting the relative positions between modules and cells, and then an initial placement are determined by the function. In order to show the usefulness of the proposed method, it was compared with clustering development method in maximum cut numbers and total routing lengths by program experiments.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.542-545
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• 2002

This paper deals with the optimization inverter design and minimization Conduced EMI noise by customizing IPM(Intelligent Power Module). Generally, In case of IPM, we realized that the trade-off relation between switching loss and spike voltage. Higher gate resistor causes tile lower spike voltage and the higher turn-off switching loss. But we know that the life cycle of inverter and the susceptibility of noise, so we optimized the gate resistor. Proposed method is that optimized the gate resistor suitable for the inverter and motor. The simulation and experimental results show that the spike voltage and Conduced EMI noise can be reduced without the additional circuit.

• Design & Manufacturing
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• v.13 no.4
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• pp.34-39
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• 2019

In this paper, in order to improve the formability and quality of the injection molded parts in the molds for molding the motorcycle rear cowl injection molded parts with different volumes at the same time, the flow of the molded parts is changed through the injection molding CAE analysis by changing the gate position, runner size and position. It is to find the optimum gate position, the diameter of the runner and the position where the balance is equal. The molded article formed by the optimization resulted in the uniformity of the molten resin at the same time at the corner of the product, thereby maintaining the flow balance favorable for mass production at lower injection pressure.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.628-635
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• 1990

This paper describes a new gate array layout system, HAN-LACAD-G(HANyang LAyout CAD system for Gate array). HAN-LACAD-G is composed of placer, global router, detailed router, and output processor. In placement design, initial placement is performed by repetitive clustering and min-cut partitioning followed by placement improvement using the concept of pairwise interchange. In global routing phase, pins are assigned in each channel considering the routing congestion estimation and overflows in feedthroughs are restricted. For the detailed routing, we use layer and three layer channel routing techniques. Layout results are displayed graphically and modified interactively by the user using the layout editor.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.647-648
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• 2006

This paper presents the design results of peripheral circuits of non-volatile memory of nano floating gate cells. The designed peripheral circuits included command decoder, decoders, sense amplifiers and oscillator, which are targeted with 0.35um technology EEPROM process for operating test and reliable test. The simulation results show each operation and test mode of output voltage for word line, bit line, well and operating of sense amplifier.

• Transactions of The Korea Fluid Power Systems Society
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• v.1 no.4
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• pp.1-8
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• 2004

The optimum design parameters of several hydraulic systems are obtained using the complex method that is one kind of constrained direct search method. First, the parameters of lead-lag controller of the direct drive servovalve is designed using the complex method to satisfy the steady-state error requirement. Second, the optimum locating point of hydraulic cylinder Is determined to minimize the cylinder force in the operation range of rotational sluice gate. For the third application case, the optimum piston area of hydraulic cylinder is determined to minimize the man power to elevate the manually operated sluice gate.