• 한국자동차공학회논문집
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• 제13권6호
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• pp.170-176
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• 2005

The hydraulic cylinder is used for actuating the sluice gate which controls the volume of water in the reservoir. The locating points of hydraulic cylinder are restricted to limited space and determined to minimize the cylinder force necessary for actuating the sluice gate. Generally, the head end point of cylinder is fixed at underground and the rod end point of cylinder is connected to the gate plate when it is fully opened. Therefore there exist three parameters to be determined to minimize the cylinder force in the operation range of sluice gate. The optimal locating points of hydraulic cylinder are obtained using the complex method that is one kind of constrained direct search m method.

• Design & Manufacturing
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• 제12권3호
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• pp.55-59
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• 2018

In a multi-cavity mold having a runner layout of a fish bone structure, problems of unbalanced filling between cavities occur constantly. Unbalanced charging lowers the dimensional accuracy of a molded article and causes deformation after molding. To solve this problem, the gate size connected to each cavity is adjusted using the BGV (Balanced Gate Value) equation. In this paper, in order to solve the filling imbalance problem of the runner layout mold of fish bone structure through injection molding analysis study, we compared the charging imbalance phenomenon before and after improvement after adjusting the gate size by applying BGV equation. From the results of the molding analysis, the shrinkage ratio before and after the improvement of the molded article was improved by only about 0.08%. Based on these results, it was confirmed that the charging imbalance problem was not significantly improved even when the BGV equation was applied.

• 한국기계가공학회지
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• 제13권6호
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• pp.73-81
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• 2014

In this paper, multiple gate locations and process conditions under concern are automatically optimized by considering robustness to minimize the injection pressure required to mold an automotive dashboard. Computer simulation-based experiments using orthogonal arrays(OA) and a design-range reduction algorithm are consolidated into an iterative search scheme, which is then used as a tool for the optimization process. The robustness of a design is evaluated using an OA-based simulation of process fluctuations due to noise as well as the signal-to-noise ratio. The optimal design solution for the automotive dashboard shows that the robustness of the injection pressure is significantly improved when compared to the initial design. As a result, both the die clamping force and the pressure distribution in the part cavity are also much improved in terms of their robustness.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.819-822
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• 1998

The high complexity of digital circuits has changed the digital circuits design mehtods from schemeatic-based to hardware description languages like VHDL, verilog that make hardware faults become more hard to detect. Thus test generation to detect hardware defects is very important part of the design. But most of the test generation methods are gate-level based. In this paper new high-level test generation method to detect stuck-at-faults on gate level is described. This test generation method is independent of synthesis results and reduce the time and efforts for test generation.

• 전자공학회논문지A
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• 제30A권8호
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• pp.57-62
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• 1993

In this paper, both feasible power gain and power added efficiency at the operating center frequency of 12 GHz are stressed to design a power FET with double-heterjunction structure. The variable parameters or the design are the unit gate width, the gate length, the doping density of AlGaAs, the AlGaAs thickness, the spacer thickness, the Al mole fraction, and the GaAs well thickness. The results of simulation for the FET with 1.mu.m gate length show that the power gain and the power added efficiency are 10.2 dB and 36.3% at 12GHz, respectively. An extrapolation of the relation between current gain and unilateral gain yields a 17 GHz cutoff frequency and 43GHz maximum frequency of oscillation. The calculation of the current versus voltage characteristics show that the output power of the device is about 0.62W.

• 한국전기전자재료학회논문지
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• 제23권4호
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• pp.273-279
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• 2010

In this paper, we proposed 2500 V Non punch-through(NPT) Insulated gate bipolar transistor(IGBT) for high voltage industry application. we carried out optimal simulation for high efficiency of 2500 V NPT IGBT according to size of device. In results, we obtaind design parameter with 375 um n-drift thickness, 15 um gate length, and 8um emitter windows. After we simulate with optimal parameter, we obtained 2840 V breakdown voltage and 3.4V Vce,sat. These design and process parameter will be used designing of more 2000 V NPT IGBT devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.156-163
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• 2008

We proposed a new $p^+/n^+$ gate locally-separated-channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of $n^+$ poly-Si gate ($L_s$), the material filling the trench, and the width and length of the trench at a given gate length ($L_g$). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent $I_{off}$ suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable $L_s/L_g$ and channel fin width ($W_{cfin}$) at given $L_gs$ of 30 nm, 40 nm, and 50 nm.

• 한국산업정보학회논문지
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• 제19권3호
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• pp.25-30
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• 2014

본 논문에서는 태양광시스템의 분산형 최대 전력점 추적(DMPPT)을 제어하는 게이트 드라이버 회로를 설계하였다. 그림자가 생긴 모듈에서도 최대 전력점을 추적할 수 있는 분산형 방식(DMPPT) 방식을 구현 하였으며, 각각의 모듈 내부에 DC-DC 변환기를 구동하기 위한 고전압 게이트 구동회로를 설계하였다. 태양광 시스템의 내부는 12비트 ADC, PLL, 게이트 드라이버가 내장 되어 있다. 게이트 드라이버의 하이 사이드 레벨 쉬프터에 숏-펄스 발생기를 추가하여 전력소모와 소자가 받는 스트레스를 줄였다. BCDMOS 0.35um 공정을 사용하여 구현하였으며 최대 2A 전류를 감달 할 수 있고, 태양 광 전압 최대 50V까지 받을 수 있도록 설계하였다.

• 전기전자학회논문지
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• 제8권1호
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• pp.22-32
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• 2004

본 논문에서는 Honghai Jiang에 의해 제안된 OVAG(Output value array graphs)를 기초로 MOVAG(Multi output value array graphs)를 이용한 다치논리함수의 구성방법을 제안하였다. D.M.Miller에 의해 제안된 MDD(Multiple-valued Decision Diagram)는 주어진 다변수의 함수에서 회로 설계까지 많은 처리시간과 노력이 요구되므로 본 논문에서는 MDD의 단점을 보완하여 데이터 처리시간의 단축과 적은 복잡도를 갖도록 MOVAG를 설계하였다. 또한 MOVAG의 구성 알고리즘과 입력행렬선정 알고리즘을 제안하고 T-gate를 사용하여 다치 논리 회로를 설계, 모의 실험을 통해 그 결과를 검증하였다.

• 전자공학회논문지SC
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• 제38권2호
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• pp.50-55
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• 2001

저 전력을 소모하는 새로운 방식의 논리회로를 설계하여 이의 성능실험을 위해 패리티체커를 구성하여 시뮬레이션 하였다. 기존의 저전력 소모용으로 설계된 논리회로(CPL, DPL, CCPL 등)들은 패스 트랜지스터를 통과하면서 약해진 신호를 풀 스윙 시키기 위해서 인버터를 사용하는데, 이 인버터가 전력소모의 주원인이 되고 있음이 본 논문에서 시뮬레이션 결과 밝혀졌다. 따라서 본 본문에서는 인버터를 사용하지 않고 신호를 풀스윙 시킬 수 있는 회로를 고안하였다. 기존의 CCPL게이트로 구성한 패리티체커에 비해 본 논문에서 제안한 게이트로 구성된 것이 33%의 전력을 적게 소모하는 것으로 시뮬레이션 결과 나타났다.