하드웨어 고장 검출을 위한 행위레벨 설게에서의 테스트패턴 생성

High level test generation in behavioral level design for hardware faults detection

The high complexity of digital circuits has changed the digital circuits design mehtods from schemeatic-based to hardware description languages like VHDL, verilog that make hardware faults become more hard to detect. Thus test generation to detect hardware defects is very important part of the design. But most of the test generation methods are gate-level based. In this paper new high-level test generation method to detect stuck-at-faults on gate level is described. This test generation method is independent of synthesis results and reduce the time and efforts for test generation.