• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.321-334
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• 2003

Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.723-726
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• 2005

GALS (Globally Asynchronous Locally Synchronous) 시스템 기반의 SoC 설계에 필수적인 DI (Delay Insensitive) 데이터 전송방식 중 기존의 전압 모드 기반 설계 방식은 N 비트 데이터 전송에 물리적으로 2N+1 개의 도선이 필요하다. 이로 인한 전력 소모와 설계 복잡성을 줄이기 위해 N+1 개의 도선으로 N 비트 데이터를 전송할 수 있는 전류 모드 다치 논리 회로 기반 설계 방식이 연구되었다. 그러나, static 전력의 비중이 커 데이터 전송 속도가 낮을수록 전력 소모 측면에서 취약하고, 휴지 모드에서도 상당량의 전력을 소비한다. 본 논문에서는 이러한 문제점을 해결할 수 있는 전류 모드 기반 인코더와 디코더 회로를 제안하고, 이에 따른 새로운 전류 인코딩 기법을 설명한다. 마지막으로 기존의 전압 모드 및 전류 모드 방식과 delay, 전력 소비 측면에서 비교 데이터를 제시한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.27-36
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• 2006

Conventional delay-insensitive (DI) data encodings usually require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, an encoder and a decoder circuits, where N-bit data transfer can be peformed with only N+l wires, are proposed. These circuits are based on a quasi delay-insensitive (QDI) model and designed by using current-mode multiple valued logic (CMMVL). The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25 um CMOS technology. In general, simulation results with wire lengths of 4 mm or larger show that the CMMVL scheme significantly reduces delay-power product ($D{\ast}P$) values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more. In addition, simulation results using the buffer-inserted dual-rail and 1-of-4 encodings for high performance with the wire length of 10 mm and 32-bit data demonstrate that the proposed CMMVL scheme reduces the D*P values of the dual-rail encoding with data rate of 4 MHz or more and 1-of-4 encoding with data rate of 25 MHz or more by up to $57.7\%\;and\;17.9\%,$ respectively.

• Asia pacific journal of information systems
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• v.8 no.3
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• pp.37-49
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• 1998

The basic goal of CALS is to improve transactions and relationships among organizations through information sharing and integration. CALS is an information strategy which needs strong cooperation between organizations or between users and developers in design step. However, current design methodologies using IDEF models, that are considered to be standard for CALS system development, has some limitations. For example, it is difficult for system developers to communicate with counterparts by IDEF model since IDEF models are difficult for counterparts to understand. In this paper, we suggest a development methodology for GALS systems by complementing IDEF model with Document Trace Diagram, which we developed as a communication tool, The concept of Document Trace Diagram stems from the fact that most information exchanged within or between organizations is in the form of documents and most standard operating procedures of organizations are about processing the documents. It helps system developers identify functions and their ICOMs (Input, Control, Output, Mechanism) with ease and little communication cost. With this methodology, we have constructed the GALS prototype system for construction industry.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.

• Proceedings of the PSK Conference
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• 2003.10b
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• pp.214.4-215
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• 2003

In galactose metabolic pathway : there are three inborn metabolic disorders galactokinase deficiency (galactosemia type II), galactose-1-phosphate uridyl transferase(GALT) daficiency (galactosemia type I ), uridine diphosphate galactose-4-epimerase deficiency (galactosemia typeIII). Among these disorders GALT deficiency is the most severe and common. Infants with GALT deficiency fail to metabolize galactose-1-phosphate. As a consequence, galactose-1-phosphate and galactose are accumulated in blood in which GALS enzyme plays the role of a pathognomonic marker. (omitted)

• Electronics and Telecommunications Trends
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• v.24 no.6
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• pp.110-120
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• 2009

비동기식 회로는 전역 클록이 없이 모듈끼리의 핸드셰이크 프로토콜에 의해 데이터를 동기화하고, 전송하는 회로로 전역 클록에 기반한 동기식 회로에 비해 전역 클록으로 인한 문제점들, 예를 들면, 타이밍 종결 문제, 전력 소모 문제, 다중 클록 도메인 설계 문제 등에서 이점을 갖는다. 최근에는 이 두 가지 회로의 장점을 모아 서로 다른 클록에 기반한 비교적 작은 규모의 동기식 모듈을 기반으로 모듈끼리의 데이터 전송을 비동기식으로 수행하는 GALS 구조도 많이 연구되고 있다. 본 고에서는 이러한 비동기식 회로를 위한 설계 방식을 설명하기 위해 먼저, 비동기식 회로의 특성과 설계 동향, 설계 방식에 영향을 미치는 핸드셰이크 프로토콜 및 지연 모델을 소개한다. 그리고, 크게 세가지의 설계 방식을 간단한 예제를 통해 설명한다.

• Geomechanics and Engineering
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• v.4 no.2
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• pp.91-103
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• 2012

Focusing on the effect of excess pore pressure dissipation on liquefaction-induced ground deformation, a series of 1-g shaking table tests were conducted in a rigid soil container by use of saturated Toyoura sand, the relative density of which was 20-60%. These tests were subjected to the sinusoidal base shaking with step increased accelerations: 100, 200, 300 and 400 Gals for 2-4 seconds. Shaking table tests were done using either water or polymer fluid with more viscous than water, thus varying the sand permeability of model tests. Excess pore pressures, accelerations, settlements and lateral deformations were measured in each test. Test results are presented in this paper and the effect of sand permeability on liquefaction and liquefaction-induced ground deformation was discussed in detail.

• Geophysics and Geophysical Exploration
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• v.13 no.1
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• pp.88-95
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• 2010

An airborne gravity survey using a helicopter was carried out in October 2008, offshore along the northern Noto Peninsula, to understand the shallow and regional underground structure. Eleven flight lines, including three tie lines, were arranged at 2 km spacing within 20 km of the coast. The total length of the flight lines was ~700 km. The Bouguer anomalies computed from the airborne gravimetry are consistent with those computed from land and shipborne gravimetry, which gradually decrease in the offshore direction. So, the accuracy of the airborne system is considered to be adequate. A local gravity low in Wajima Bay, which was already known from seafloor gravimetry, was also observed. This suggests that the airborne system has a structural resolution of ~2 km. Reduction of gravity data to a common datum was conducted by compiling the three kinds of gravity data, from airborne, shipborne, and land surveys. In the present study, we have used a solid angle numerical integration method and an iteration method. We finally calculated the gravity anomalies at 300 m above sea level. We needed to add corrections of 2.5 mGals in order to compile the airborne and shipborne gravity data smoothly, so the accuracy of the Bouguer anomaly map is considered to be nearly 2 mGal on the whole, and 5 mGals at worst in limited or local areas.