• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.11a
• /
• pp.303-304
• /
• 2005

In this paper, we report a fluxless eutectic die bonding process which uses 80Au-20Sn eutectic alloy. The chip LEDs are picked and placed on silicon substrate wafers. The bonding process temperatures and force are $305\sim345^{\circ}C$ and 10$\sim$100gf, respectively. The bonding process was performed on graphite heater with nitrogen atmosphere. The quality of bonding are evaluated by shear test and thermal resistance. Results of fluxless eutectic die bonding show that shear strength is Max. 3.85kgf at 345$^{\circ}C$ /100gf and thermal resistance of junction to die bonding is Min. 3.09K/W at 325$^{\circ}C$/100gf.

• The KIPS Transactions:PartA
• /
• v.15A no.3
• /
• pp.161-166
• /
• 2008

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF($2^m$) using the polynomial basis representation. The proposed systolic array is based on the most significant digit first (MSD-first) multiplication algorithm and produces multiplication results at a rate of one every "m/D" clock cycles, where D is the selected digit size. Since the inner structure of the proposed multiplier is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of a high regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.

• The KIPS Transactions:PartA
• /
• v.9A no.3
• /
• pp.281-286
• /
• 2002

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

• Korean Journal of Fisheries and Aquatic Sciences
• /
• v.47 no.2
• /
• pp.135-143
• /
• 2014

Exopeptidase active fractions from the hepatopancreas of the Argentina shortfin squid Illex argentinus, were obtained with acetone (AC 30-40%), ammonium sulfate (AS 60-70% saturation), anion exchange chromatography (AE-II, 0.2 M NaCl) and gel filtration chromatography (GF-I, 30-50 kDa) fractionation methods. A bitter peptide solution that has a bitterness equivalent to that of 2% glycylphenylalanine and prepared by tryptic hydrolysis of milk casein, was treated with the exopeptidase active fractions. The GF-I fraction was the best based on aminopeptidase activity (35.3 U/mg), percentage of recovery (30.7%) and a sensory evaluation (1.7). The amount of released amino acids increased as incubation time increased, and the bitterness of the enzyme reaction mixtures decreased. Incubation with the GF-I fraction for 24 h resulted in the hydrolysis of several peptides as revealed by the reverse-phase high performance liguid chromatography profile, with three peaks (3, 5 and 6) decreasing in area (%) and three peaks (1, 2 and 4) increasing in area (%). Therefore, the GF-I fraction appeared to be ideally suited to reduce bitterness in protein hydrolysates by catalyzing the hydrolysis of bitter peptides.

• Journal of the Korea Society of Computer and Information
• /
• v.17 no.3
• /
• pp.1-10
• /
• 2012

A low-complexity Multiplication over GF(2m) and multiplier circuit has been proposed by using cyclic-shift coefficients and the irreducible trinomial. The proposed circuit has the parallel input/output architecture and shows the lower-complexity than others with the characteristics of the cyclic-shift coefficients and the irreducible trinomial modular computation. The proposed multiplier is composed of $2m^2$ 2-input AND gates and m (m+2) 2-input XOR gates without the memories and switches. And the minimum propagation delay is $T_A+(2+{\lceil}log_2m{\rceil})T_X$. The Proposed circuit architecture is well suited to VLSI implementation because it is simple, regular and modular.

• Maxillofacial Plastic and Reconstructive Surgery
• /
• v.13 no.3
• /
• pp.252-264
• /
• 1991

The purpose of this study was to compare the response of adjacent tissue and new bone formation after implantation by different methods of subperiosteal using using Proplast I and II in rabbit mandible. Microstructure of Proplast I and II was observed by scanning electron microscope. And the implantation procedure was carried out by dividing into tow groups, A and B. a group consisted of subperiosteal graft on the cortex, and the other B group was made up onlay graft following artificial decortication in the madibular body of rabbit. The experimental animals were sacrificed on the 1st, 2nd, 4th and 8th week after grafting for macroscopic and histopathologic examination. The samples extracted at the 6th postgrafting week were also used for biometric test. The result ere as follows : 1. By scanning electron microscopic observation, pore size was $50{\sim}180{\mu}m$ in the Proplast I and $100{\sim}220{\mu}m$ in Proplast II. 2. Macroscopically, infection of the graft site, deformation and displacement of the implanted materials were not observed in all experimental groups. 3. In the tissue response, infiltration of inflammatory cells and multinucleated giant cells were observed from the 2nd to the 8th week in Proplast I. Inflammatory cells decreased in number from the 2nd week in Proplast II suggesting that Proplast II is better than Proplast I. 4. Bone formation was not observed until the 8th week in the group A, but new bone formation from the surrounding graft bed and the periostium was appeared from the 4th week in the group B. 5. The maximum mean values of shear stress mere serially $65.5gf/mm^2$ in Proplast II of group B, $32.9gf/mm^2$ in Proplast I of group B, $17.0gf/mm^2$ in Proplast II of group A, and $15.7gf/mm^2$ in Proplast I. of group A.

• Journal of IKEEE
• /
• v.23 no.1
• /
• pp.58-67
• /
• 2019

A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.3
• /
• pp.419-426
• /
• 2021

A high-performance elliptic curve cryptography processor (HP-ECCP) was designed to support five field sizes of 192, 224, 256, 384 and 521 bits over GF(p) defined in NIST FIPS 186-2, and it provides eight modes of arithmetic operations including ECPSM, ECPA, ECPD, MA, MS, MM, MI and MD. In order to make the HP-ECCP resistant to side-channel attacks, a modified left-to-right binary algorithm was used, in which point addition and point doubling operations are uniformly performed regardless of the Hamming weight of private key used for ECPSM. In addition, Karatsuba-Ofman multiplication algorithm (KOMA), Lazy reduction and Nikhilam division algorithms were adopted for designing high-performance modular multiplier that is the core arithmetic block for elliptic curve point operations. The HP-ECCP synthesized using a 180-nm CMOS cell library occupied 620,846 gate equivalents with a clock frequency of 67 MHz, and it was evaluated that an ECPSM with a field size of 256 bits can be computed 2,200 times per second.

• Journal of Welding and Joining
• /
• v.19 no.2
• /
• pp.176-181
• /
• 2001

Reflow soldering characteristics of Sn-3.5Ag and Sn-37Pb balls for BGA(Ball grid Array) were investigated. Diameter of 0.76mm ball was set on a Cu/Ni/Au-coated pad and reflowed in air with changing peak soldering temperature and conveyor speed. Peak temperatures were changed from 240 to 28$0^{\circ}C$ for Sn-3.5Ag, and from 220 to 26$0^{\circ}C$ for Sn-37Pb balls. As results, heights of solder balls increased and widths decreased with peak soldering temperature. Through aging treatment at 10$0^{\circ}C$ for 1.000 hrs, average hardness of Sn-3.5Ag balls bonded at 25$0^{\circ}C$ cecreased from 14.90Hv to 12.83Hv And with same aging conditions, average shear strength of Sn-3.5Ag balls bonded at 26$0^{\circ}C$ decreased from 1727gf to 1650gf.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.38 no.1
• /
• pp.27-34
• /
• 2001

The multiplication algorithm using the primitive irreducible trinomial $x^m+x+1$ over $GF(2^m)$ was proposed by Mastrovito. The multiplier proposed in this paper consisted of the multiplicative operation unit, the primitive irreducible operation unit and mod operation unit. Among three units mentioned above, the Primitive irreducible operation was modified to primitive irreducible trinomial $x^m+x+1$ that satisfies the range of 1$x^m,{\cdots},x^{2m-2}\;to\;x^{m-1},{\cdots},x^0$ is reduced. In this paper, the primitive irreducible polynomial was reduced to the primitive irreducible trinomial proposed. As a result of this reduction, the primitive irreducible trinomial reduced the size of circuit. In addition, the proposed design of multiplier was suitable for VLSI implementation because the circuit became regular and modular in structure, and required simple control signal.