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http://dx.doi.org/10.6109/jkiice.2021.25.3.419

A High-Performance ECC Processor Supporting Multiple Field Sizes over GF(p)  

Choe, Jun-Yeong (School of Electronic Engineering, Kumoh National Institute of Technology)
Shin, Kyung-Wook (School of Electronic Engineering, Kumoh National Institute of Technology)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.25, no.3, 2021 , pp. 419-426 More about this Journal
Abstract
A high-performance elliptic curve cryptography processor (HP-ECCP) was designed to support five field sizes of 192, 224, 256, 384 and 521 bits over GF(p) defined in NIST FIPS 186-2, and it provides eight modes of arithmetic operations including ECPSM, ECPA, ECPD, MA, MS, MM, MI and MD. In order to make the HP-ECCP resistant to side-channel attacks, a modified left-to-right binary algorithm was used, in which point addition and point doubling operations are uniformly performed regardless of the Hamming weight of private key used for ECPSM. In addition, Karatsuba-Ofman multiplication algorithm (KOMA), Lazy reduction and Nikhilam division algorithms were adopted for designing high-performance modular multiplier that is the core arithmetic block for elliptic curve point operations. The HP-ECCP synthesized using a 180-nm CMOS cell library occupied 620,846 gate equivalents with a clock frequency of 67 MHz, and it was evaluated that an ECPSM with a field size of 256 bits can be computed 2,200 times per second.
Keywords
Elliptic curve cryptography (ECC); Point scalar multiplication; Prime field elliptic curve; Karatsuba-Ofman algorithm; Lazy reduction algorithm;
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