• Journal of IKEEE
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• v.25 no.1
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• pp.15-24
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• 2021

In this paper, 1700 V EPDT (Extended P+ shielding floating gate Double Trench) MOSFET structure, which has a smaller switching time and loss than CDT (Conventional Double Trench) MOSFET, is proposed. The proposed EPDT MOSFET structure extended the P+ shielding area of the source trench in the CDT MOSFET structure and divided the gate into N+ and floating P- polysilicon gate. By comparing the two structures through Sentaurus TCAD simulation, the on-resistance was almost unchanged, but Crss (Gate-Drain Capacitance) decreased by 32.54 % and 65.5 %, when 0 V and 7 V was applied to the gate respectively. Therefore, the switching time and loss were reduced by 45 %, 32.6 % respectively, which shows that switching performance was greatly improved.

• Journal of Environmental Science International
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• v.14 no.11
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• pp.995-1004
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• 2005

As a research establish reservoir safety operation for small dam systems. This study presents hydrologic analysis conducted in the Duckdong and Bomun dam watershed based on various rainfall data and increase inflow. Especially the Duckdong dam without flood control feature are widely exposed to the risk of flooding, thus it is constructed emergency gate at present. In this study reservoir routing program was simulation for basin runoff estimating using HEC-HMS model, the model simulation the reservoir condition of emergency Sate with and without. At the reservoir analysis results is the Duckdong dam average storage decrease $20\%$ with emergency gate than without emergency gate. Also, the Bomun dam is not affected by the Duckdong flood control augmentation.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.9 no.6
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• pp.21-28
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• 2010

This study shows an optimization procedure for an automatic determination on the gate position to ensure the fill-uniformity within a part cavity by using the injection molding simulation. For an optimization, the maximum pressure-difference within a part cavity induced at the stage of filling is used to evaluate degree of fill-uniformity. In addition, a direct search scheme based on the reduction of design space is developed and applied in the optimization problem. This corresponding proposed methodology was applied in the optimization on the gate location for a CD-tray molding, as a result, showed the improvement of the fill-uniformity within the cavity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.137-140
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• 1998

An active-matrix LCD using thin film transistors (TFT) has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate si후미 distortion and pixel charging capability. which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the resistivity of gate line material on the pixel operations can be effectively analyzed. The gate signal delay, pixel charging ratio and level-shift of the pixel voltage were simulated with varying the parameters. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.5
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• pp.263-267
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• 2016

In this paper, we analyzed the electrical characteristics of NPT planar and trench gate IGBT after designing these devices according to design and process parameter. To begin with, we have designed NPT planar gate IGBT and carried out simulation with T-CAD. Therefore, we extracted design and process parameter and obtained optimal electrical characteristics. The breakdown voltage was 724 V and The on state voltage drop was 1.746 V. The next was carried out optimal design of trench gate power IGBT. We did this research by same drift thickness and resistivity of planar gate power IGBT. As a result of experiment, we obtain 720 V breakdown voltage, 1.32 V on state voltage drop and 4.077 V threshold voltage. These results were improved performance and fabrication of trench gate power IGBT and planar gate Power IGBT.

• Journal of IKEEE
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• v.19 no.4
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• pp.514-519
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• 2015

We propose the multiple gate structure of double gate junctionless metal oxide silicon field oxide transistor (JL MOSFET) for device optimization. Since different workfunction within multiple metal gates, electric potential nearby source and drain region is modulated in accordance with metal gate length. On current, off current and threshold voltage are influenced with gate structure and make possible to meet some device specification. Through the device simulation work, performance optimization of double gate JL MOSFETs are introduced and investigated.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.1974-1976
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• 2005

The feasibility of a midgap metal gate is investigated for 32nm MOSFET low power applications. The midgap metal gate MOSFET is found to deliver a driving current as high as a bandedge gate one for the low power applications if a proper retrograde channel is used. An adequate design of the retrograde channel is essential to achieve the performance requirement given in ITRS roadmap. In addition, a process simulation is run using halo implants and thermal processes to evaluate the feasibility of the necessary retrograde profile in manufacturing environments. From the thermal budget point of view, the bandedge metal gate MOSFET is more vulnerable to the following thermal process than the midgap metal gate MOSFET since it requires a steeper retrograde doping profile. Based on the results, a guideline for the gate workfunction and the channel profile in the 32 nm MOSFET is proposed.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1577-1580
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• 1987

This paper proposes a gate and functional level logic simulator which can be run on XENIX O.S. The simulator has hierarchical structure including Hardware Description Language compiler, Waveform Description Language compiler, and Simulation Command Language compiler. The Hardware Description Language compiler generates data structure composed of gate structure, wire structure, condition structure, and event structure. Simulation algorithm is composed of selective trace and event-driven methods. To improve simulation speed, Cross Referenced Linked List Structure ia defined in building the data structure of circuits.

• Journal of Korean Society of Water and Wastewater
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• v.25 no.3
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• pp.349-357
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• 2011

This study has an objective to estimate effect on water-quality enhancement by removal of contaminated river-bed material using a two-dimensional numerical modeling in the Seonakdong River, the Pyunggang River and the Maekdo River. RMA2 and RMA4 models were used for flow and contaminant transport simulation, respectively. After the analysis of the effects of flow restoration plan for the Seonakdong River system made by Lee et al (2008), simulation have been performed about scenarios which contains operations of the Daejeo Gate, the Noksan Gate, the Makdo Gate (on planning), and the Noksan Pumping Station. Because there is no option for elution from bed sediment in the RMA4 model, a simple technique has been used for initial condition modification for elution. The analyses revealed that the effect on water quality improvement due to dredging of bed sediment seemed to be less than 10 % of the total effect. The most efficient measure for the water quality improvement of the river system was the linked operation of water-gates and pumping station.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.655-661
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• 2014

In this paper, a new two dimensional (2D) analytical modeling and simulation for a surrounding gate tunnel field effect transistor (TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunneling generation rate and thus we numerically extract the tunneling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.