• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.1-6
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• 2002

For an optimum device design of nano-scale SOI devices, this paper describes the short channel effects of multi-gate structures SOI MOSFETs such as double gate, triple gate and quadruple gate, as well as a new proposed Pi gate using computer simulation. The simulation has been performed with different channel doping concentrations, channel widths, silicon film thickness, and vertical gate extension depths of Pi gate. From the simulation results, it is found that Pi gate devices have a large margin in determination of doping concentrations, channel widths and film thickness comparing to double and triple gate devices because Pi gate devices offer a better short channel effects.

• Journal of Navigation and Port Research
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• v.31 no.9
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• pp.771-778
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• 2007

A container terminal gate is not only an entrance of containers, but also the first input point of containers' information. Therefore, to achieve the accuracy of container information, there are various containers' numbers recognition methods used. Gate productivity can significantly vary depending upon those recognition methods. Recently, RFID which is one of the u-IT businesses run by the Korean government is under consideration for application to the gate as an automatic system. If RFID is used, it is expected to have both the qualitative benefits through avoiding defects of other systems and the quantitative benefits by improving productivity. Hence, this study aims to provide some insight on the benefits of RFID, and to compare productivity of the existing gate system with the RFID gate system based on computer simulation.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.67-88
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• 2005

Mold-Flow 3 Die Stack CSP of Mold array packaging with different Gate types. As high density package option such as 3 or 4 die stacking technologies are developed, the major concerning points of mold related qualities such as incomplete mold, exposed wires and wire sweeping issues are increased because of its narrow space between die top and mold surface and higher wiring density. Full 3D rheokinetic simulation of Mold flow for 3 die stacking structure case was done with the rheological parameters acquired from Slit-Die rheometer and DSC of commercial EMC. The center gate showed severe void but corner gate showed relatively better void performance. But in case of wire sweeping related, the center gate type showed less wire sweeping than corner gate types. From the simulation results, corner gate types showed increased velocity, shear stress and mold pressure near the gate and final filling zone. The experimental Case study and the Mold flow simulation showed good agreement on the mold void and wire sweeping related prediction. Full 3D simulation methodologies with proper rheokinetic material characterization by thermal and rheological instruments enable the prediction of micro-scale mold filling behavior in the multi die stacking and other complicated packaging structures for the future application.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.133-137
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• 2017

The purpose of this study was to validate for GATE (Geant4 Application for Tomographic Emission) simulation by comparing the results of GATE simulation and experiment in real SPECT system. Futhermore, we want to prove that it is possible that the quantitative research of gamma camera/SPECT imaging for therapeutic radio isotope by using GATE simulation. In this study, the SPECT system on simulation referred to the parameters of Stream-R Forte version 1.2 (Philips Medical System, Best and Heerlen, Netherlands). To understand the I-131 image of gamma camera/SPECT system, we acquired the energy spectrum and measured the full width at half maximum (FWHM) which comes from line spread function (LSF) with and without scatter material in real SPECT system. And to compare with experiment, we also measured the FWHM and acquired the energy spectrum without scatter material in GATE simulation. As a result, without scatter material, the energy peak was almost same location, which are located nearby 364 keV, and other spectrum factors are same tendency in both cases. The FWHM was increased by increasing the distance of source to detector, and the error rate was approximately 3.8%. When we used the line source with scatter material, energy spectrum also indicated similar tendency in both cases. As you confirmed earlier, GATE simulation included real instrument and radioisotope characters for therapeutic radioisotope. Therefore this result that it was possible that various quantitative study for therapeutic radioisotope imaging in gamma camera/SPECT using GATE simulation.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.579-580
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• 2006

Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.36 no.4
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• pp.71-76
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• 2013

For a die casting mold, generally, the casting layout design should be considered based on the relation among injection system, casting condition, gate system, and cooling system. Also, the extent or the location of product defects was differentiated according to the various relations of the above conditions. In this research, in order to optimize the casting layout design of an automotive Oil Pan_DX2E, Computer Aided Engineering (CAE) simulation was performed with two layout designs by using the simulation software (AnyCasting). The simulation results were analyzed and compared carefully in order to apply them into the production die-casting mold. During the filling process with two models, internal porosities caused by air entrapments were predicted and also compared with the modification of the gate system and overflow. With the solidification analysis, internal porosities occurring during the solidification process were predicted and also compared with the modified gate system.

• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• Journal of the Korean Society of Radiology
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• v.1 no.3
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• pp.11-16
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• 2007

In this study, the potential of a newly developed simulation toolkit, GATE for the simulation of electronic portal imaging devices (EPID) in radiation therapy was evaluated by characterizing the performance of the metal plate/phosphor screen detector for EPID. We compared the performances of the GATE simulator against MCNP4B code and experimental data obtained with the EPID system in order to validate its use for radiation therapy.

• Journal of Navigation and Port Research
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• v.40 no.6
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• pp.421-430
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• 2016

In this study, a gate simulation model was developed to reduce the truck waiting time for trucking companies servicing container terminals. To verify the developed model, 4 weeks of truck gate-in/gate-out data was collected in December 2014 at the Port of Busan New Port. Also, the existing gate system was compared to the proposed gate system using the developed simulation model. The result showed that based on East gate-in, a maximum number of 50 waiting trucks with a maximum waiting time of 120 minutes. With the proposed system the maximum number of waiting trucks was 10 with a maximum waiting time of 5.3 minutes. Based on West gate-in, the maximum number of waiting trucks was 17 and the maximum waiting time was 34 minutes in the existing gate system. With the proposed system the maximum number of waiting trucks was 10 with a maximum waiting time of 5.3 minutes. Based on West gate-out, the maximum number of waiting trucks was 11 with a maximum waiting time of 5.5 minutes. With the proposed system the maximum number of waiting trucks was 9 with a maximum waiting time of 4.4 minutes. This developed model shows how many waiting trucks there are, depending on the gate-in/gate-out time of each truck. This system can be used to find optimal gate system operating standards by assuming and adjusting the gate-in/gate-out time of each truck in different situations.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1809-1811
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• 1999

In recent years, attempts have been made to greatly improve the display quality of active-matrix liquid crystal display devices, and many techniques have been proposed to solve such problems as gate delay, feed-through voltage and image sticking. Gate delay is one of the biggest limiting factors for large-screen-size, high-resolution thin-film transistor liquid crystal display (TFT/LCD) design. Many driving method proposed for TFT/LCD progress. Thus we developed gate driving signal generator. Since Pixel-Design Array Simulation Tool (PDAST) can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the driving signals of gate lines on the pixel operations can be effectively analyzed.