• 한국전기전자재료학회논문지
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• 제28권11호
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• pp.698-703
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• 2015

In this study, we fabricated the dual gate (DG) ion-sensitive field-effect-transistor (ISFET) with flexible polyimide (PI) extended gate (EG). The DG ISFETs significantly enhanced the sensitivity of pH in electrolytes from 60 mV/pH to 1152.17 mV/pH and effectively improved the drift and hysteresis phenomenon. This is attributed to the capacitive coupling effect between top gate and bottom gate insulators of the channel in silicon-on-transistor (SOI) metal-oxide-semiconductor (MOS) FETs. Accordingly, it is expected that the PI-EG based DG-ISFETs is promising technology for high-performance flexible biosensor applications.

• 한국자동차공학회논문집
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• 제14권4호
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• pp.192-198
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• 2006

The real-time simulator of a turning-type sluice gate actuated by the hydraulic cylinders is developed using a PC and a visual C++ program language. The real-time simulator receives the directional control valve signal selected by the operator using the mouse, updates the state variables of the turning-type sluice gate system responding to the control signal, and draws the moving figures of the sluice gate, cylinder, reserved water every drawing time on the PC monitor. Also, the operator can observe the sluice gate angle, cylinder force, cylinder pressures, and hydraulic power representing the operation of sluice gate system through the PC monitor every drawing time. The simulator can be a very useful tool to design and improve the turning-type sluice gate system.

• 전력전자학회논문지
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• 제4권2호
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• pp.111-121
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• 1999

대용량 IGBT를 위한 새로운 능동 게이트 구동회로를 제안한다. IGBT의 우수한 스위칭 성능을 성취하기 위해 필요한 여러 구동 조건들을 최적으로 조합시킨 게이트 구동 회로이다. 스위칭 노이즈와 스트레스를 감소시키기 위해 필요한 느린 구동 조건과 스위칭 속도를 증가시키고 손실을 저감시키기 위해 요구되는 고속 구동 조건들을 동시에 만족시키고 있다. 또한 작은 전류의 턴-온시 발생되는 진동현상을 효과적으로 감쇠시킬 수 있는 특성을 지니고 있다.

• Transactions on Electrical and Electronic Materials
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• 제14권1호
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• pp.28-31
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• 2013

A volcano shaped gated Si-FEA (silicon field emitter array) was simply fabricated using sputtering as a gate electrode deposition and lift-off for the removal of the oxide mask, respectively. Due to the limited step coverage of well-controlled sputtering and the high aspect ratio in Si dry etch caused by high RF power, it was possible to obtain Si FEAs with a stable volcano shaped gate structure and to realize the restriction of gate leakage current in field emission characteristics. For 100 tip arrays and 625 tip arrays, gate leakage currents were restricted to less than 1% of the anode current in spite of the volcano-shaped gate structure. It was also possible to keep the emitters stable without any failure between the Si cathode and gate electrode in field emission for a long time.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2001년도 학술대회논문집
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• pp.39-46
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• 2001

The plasma display panel with the electrode structure of new discharge AND gate was developed and the driving system for experiment was developed. And discharge AND gate operation was verified. Discharge AND gate operated by the operation speed of 8$mutextrm{s}$ and the operation margin of 20V. It was known to be able to control the discharge of the adjoining scan electrode accurately. Because this method uses the DC discharge, the control of the discharge can be facilitated compared with conventional discharge AND gate. Moreover, because the imput discharge and the output discharge of AND gate are separate, the display discharge can be prevented from passing AND gate. Therefore, it is possible to apply to the large screen plasma display. And the decrease of contrast ratio does not occur because the scanning electrical discharge does not influence the picture quality.

• 한국전기전자재료학회논문지
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• 제26권10호
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• pp.720-725
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• 2013

Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have analyzed trench process, field limit ring process for fabrication of unified trench gate power MOSFET. And we have analyzed electrical characteristics of fabricated unified trench gate power MOSFET. The optimal trench process was based on SF6. After we carried out SEM measurement, we obtained superior trench gate and field limit ring process. And we compared electrical characteristics of planar and trench gate unified power MOSFET after completing device fabrication. As a result, the both of them was obtained 500 V breakdown voltage. However trench gate unified power MOSFET was shown improved Vth and on state voltage drop characteristics than planar gate unified power MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.41-45
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• 2012

We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• 반도체디스플레이기술학회지
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• 제14권2호
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• 한국전기전자재료학회논문지
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• 제29권5호
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• pp.263-267
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• 2016

In this paper, we analyzed the electrical characteristics of NPT planar and trench gate IGBT after designing these devices according to design and process parameter. To begin with, we have designed NPT planar gate IGBT and carried out simulation with T-CAD. Therefore, we extracted design and process parameter and obtained optimal electrical characteristics. The breakdown voltage was 724 V and The on state voltage drop was 1.746 V. The next was carried out optimal design of trench gate power IGBT. We did this research by same drift thickness and resistivity of planar gate power IGBT. As a result of experiment, we obtain 720 V breakdown voltage, 1.32 V on state voltage drop and 4.077 V threshold voltage. These results were improved performance and fabrication of trench gate power IGBT and planar gate Power IGBT.