• Journal of architectural history
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• v.29 no.3
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• pp.51-66
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• 2020

Paldalmun gate was built in 1794 as the southern gate of Suwon Hwaseong. The signboard's paintworks of Paldalmun gate was applied to the signboard of the state-run building in the 18th century. The signboard of Paldalmun gate was repainted along with the building when repaired in 1969. In that time, the signboard's paintworks during the reign of Jeongjo era was transformed. The purpose of this study is to restore the image of Jeongjo era paintworks on the Paldalmun's signboard, which has been modified since the 1960s due to modification. For the purpose of the examination, we examined the traces of paintworks remaining on the signboard of Paldalmun gate and examined several state-run signboards decorated with 'Yukhwamoon' paintings similar as the signboard of Paldalmun gate, which made around the 18th century. Through the above-mentioned researches, typical color features were identified in the decorated with 'Yukhwamoon' paintings on signboard in the 18th and 19th centuries. In addition, the type of pigment used in the signboard's paintwork of Paldalmun gate was verified through the 『Hwaseong Seongyeok Uigwe(華城城役儀軌)』 and the 『Han-gul Jeongri Uigwe(한글整理儀軌)』, while analyzing the characteristics of age-related deterioration according to the type of paintworks in various traces of pigment coatings remaining on the signboard of Paldalmun gate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.224-236
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• 2013

This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.

• Journal of the Korean Magnetics Society
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• v.12 no.4
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• pp.149-153
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• 2002

Flux-gate magnetometer has been still used for low field magnetic field measurement with portability, low power consumption, and high reliability. In many applications, flux-gate magnetometer measures not absolute values but changes of the earth magnetic field. For the eia magnetic field change measurements, we have constructed a high sensitive 3-axis flux-gate magnetometer of which measuring ranges is ${\pm}$1000 nT and noise level is 5pT/√㎐ at 1 ㎐. Using this magnetometer, we can compensate the earth magnetic field of ${\pm}$50,000 nT with successive approximation methods using microcomputer. After earth magnetic field compensation, we could measure earth magnetic field changes with ${\pm}$100 nT measuring ranges.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.4
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• pp.253-260
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• 2012

IGBT (insulated gate bipolar transistor) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the on state voltage drop should be lowered and the switching time should be shorted. However, there is Trade-off between the breakdown voltage and the on state voltage drop. To achieving good electrical characteristics, field stop IGBT (FS IGBT) is proposed. In this paper, 1,200 V planar gate non punch-through IGBT (planar gate NPT IGBT), planar gate FS IGBT and trench gate FS IGBT is designed and optimized. The simulation results are compared with each three structures. In results, we optain optimal design parameters and confirm excellence of trench gate FS IGBT. Experimental result by using medici, shows 40% improvement of on state voltage drop.

• Journal of the Korean Society of Safety
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• v.32 no.2
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• pp.85-91
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• 2017

When the shell-type roller gate is partly open, at a certain height the large vibration is caused due to resonance and the vibration can cause damage to the gate. In this study, the review on amplitude of vibration and the possible resonance occurring at the time of opening or closing of gate is performed. Throughout the natural frequency analysis, the installation location of the measuring instrument was selected. On opening or closing of gate, the measurement of gate vibration is performed. The natural frequencies according to the opening range of the gate is analyzed. As a result of measurement and analysis, we proposed ranges in which vibration occurs largely and resonance is predicted as an avoiding open ranges, or the safe opening or closing of the shell-type roller gate. The application of this paper's avoiding open range estimation method of shell-type roller gate can be utilized as the basic data for the systematic and rational maintenance management of dams and submerged weirs in the future, and it is expected that this study can bring forth.

• Journal of Korea Water Resources Association
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• v.37 no.8
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• pp.675-685
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• 2004

In this study, overflow behaviors through a partially open tainter gate mounted on a standard ogee spillway were investigated by using the FLOW-3D. The results indicated that the discharge coefficient is in the range of 0.685 to 0.723. A relation of gate-controlled discharge to free discharge was proposed and a reasonable correlation between the free and controlled discharge was obtained. Pressures on the spillway crest and the gate were also investigated. As the gate opening rate decreases with a fixed gate opening height and the gate opening height increases at a fixed gate opening rate, negative pressures on the spillway crest and the dimensionless maximum pressures on the gate increase.

• Journal of Information Display
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• v.7 no.3
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• pp.27-30
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• 2006

This paper presents a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_{2}O_{3}$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_{2}O_{3}$ as both a top gate dielectric and a passivation layer was investigated. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric was changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_{2}O_{3}$ as a top gate dielectric was changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode was changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure was successfully investigated by an analysis of electrostatic potential.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.31-39
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• 2001

W polymetal gate technology for giga bit DRAM are presented. Key module processes for polymetal gate are studied in detail. $W/WN_x/poly-silicon$ adopted for a word line of 256Mbit DRAM has good gate oxide integrity and junction leakage characteristics through full integration, which is comparable to those of conventional $WSi_x$/Poly-silicon gate process. These results undoubtedly show that $W/WN_x/poly-silicon$ is the strongest candidate as a word line for Giga bit DRAM.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.691-694
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• 2003

Density gradient method is used to analyze the quantum effect in MOSFET, Quantization effect in the poly gate leads to a negative threshold voltage shift, which is opposed to the positive shift caused by quantization effect in the channel. Quantization effects in the poly gate are investigated using the density gradient method, and the impact on the short channel effect of double gate device is more significant.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.632-642
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• 2017

This paper presents an improved approach towards reducing the switching loss of insulated gate bipolar transistors (IGBTs) for a medium-capacity-class power conditioning system (PCS). In order to improve the switching performance, the switching operation is analyzed, and based on this analysis, an improved switching method that reduces the switching time and switching loss is proposed. Compared to a conventional gate drive scheme, the switching loss, switching time, and delay are improved in the proposed gate driving method. The performance of the proposed gate driving method is verified through several experiments.