• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1914-1924
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• 2014

In this paper, a small-area cell array method of reducing number of SL drivers requiring large layout areas, where the SL drivers supplying programming currents are routed in the row direction in stead of the column direction for eFuse OTP memory IPs having less number of rows than that of columns such as a cell array of four rows by eight columns, and a core circuit are proposed. By adopting the proposed cell array and core circuit, the layout area of designed 32-bit eFuse OTP memory IP is reduced. Also, a V2V ($=2V{\pm}10%$) regulator necessary for RWL driver and BL pull-up load to prevent non-blown eFuse from being blown from the EM phenomenon by a big current is designed. The layout size of the designed 32-bit OTP memory IP having a cell array of four rows by eight columns is 13.4% smaller with $120.1{\mu}m{\times}127.51{\mu}m$ ($=0.01531mm^2$) than that of the conventional design with $187.065{\mu}m{\times}94.525{\mu}m$ ($=0.01768mm^2$).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2359-2368
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• 2013

In this paper, an IRD (internal read data) circuit preventing the reentry into the read mode while keeping the read-out DOUT datum at power-up even if noise such as glitches occurs at signal ports such as an input signal port RD (read) when a power IC is on, is proposed. Also, a pulsed WL (word line) driving method is used to prevent a DC current of several tens of micro amperes from flowing into the read transistor of a differential paired eFuse OTP cell. Thus, reliability is secured by preventing non-blown eFuse links from being blown by the EM (electro-migration). Furthermore, a compared output between a programmed datum and a read-out datum is outputted to the PFb (pass fail bar) pin while performing a sensing margin test with a variable pull-up load in consideration of resistance variation of a programmed eFuse in the program-verify-read mode. The layout size of the 8-bit eFuse OTP IP with a $0.18{\mu}m$ process is $189.625{\mu}m{\times}138.850{\mu}m(=0.0263mm^2)$.

• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.976-978
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• 1998

In this paper, we designed basic concept and structure of bypassing device which promoted the activity of low voltage line-fuse, when it perceived the too small short-fault current to activate line-fuse which located at the between secondary of pole transformer and home immediately. And we study displacement of bypass contact and electromagnetic force caused by the short-fault current by the basic experiment to understand the basic characteristic of bypassing movements.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.132-135
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• 2001

To improve the fault coordination of underground distribution line we study the several contents such as the magnitude of fault current in distribution line tripping time of CB by acting of over current relay with instantaneous trip and time delay trip. We also examine the melting time of current limiting fuse inside power fuse Through the research as above. we suggest the modification scheme of fault coordination to reduce the interruption times of power failure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.115-122
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• 2014

In this paper, reliability is secured by sensing a post-program resistance of several tens of kilo ohms and restricting a read current flowing over an unblown eFuse within $100{\mu}A$ since RWL driver and BL pull-up load circuits using a regulated voltage of V2V ($=2V{\pm}10%$) are proposed to have a wide operating voltage range for eFuse OTP memory. Also, when a comparison of a cell array of 1 row ${\times}$ 32 columns with that of 4 rows ${\times}$ 8 columns is done, the layout size of 4 rows ${\times}$ 8 columns is smaller with $187.065{\mu}m{\times}94.525{\mu}m$ ($=0.01768mm^2$) than that of 1 row ${\times}$ 32 columns with $735.96{\mu}m{\times}61.605{\mu}m$ ($=0.04534mm^2$).

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1153-1155
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• 1993

This paper presents some experimental result of current limiting, fusing and short circuit interruption behavior by notch construction of thin copper film $35{\mu}m$ on epoxy substrate. A fuse-link having elements of copper film provided high-precision small holes by photo eatching process.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.10
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• pp.31-36
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• 2018

Fuses are used to protect electric circuits or devices from excess current. Glass-tube fuses are typically used, but problems have arisen due to the mandated switch from conventional solder to lead-free solder. This study used CFD to simulate the phenomenon of molten solder being poured out of a fuse during the soldering process for a fuse cap and fuse element. In addition, a method is proposed to prevent solder from overflowing, and its effectiveness was verified based on the analysis results. The results show that a sufficient increase of the temperature inside the glass tube before soldering and gravity can help to prevent the solder from overflowing.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2007.11a
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• pp.1415-1418
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• 2007

When a high voltage COS fuse becomes a short circuit by the over current, the impulse noise over 150 dB(A) with the strong pulse jet is radiated from the COS fuse of an electric transformer. For the purpose of the impulse noise reduction, in this study, a reactive type silencer with perforated panels are considered. The transmission loss of the silencer are calculated by transfer matrix method. The effect of the porosity, the distance between panels, and the number of perforated panel on the sound transmission loss is investigated and discussed.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.762-764
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• 1992

This Paper presents some experimental result of current limiting and short circuit interruption behavior of thin copper film, 12${\mu}m$, 25${\mu}m$, 40${\mu}m$, 50${\mu}m$ on alumina substrate. and a fuse-link having elements of copper film provided with high-precision small hols with electrolytical process. Construction, fabrication, as well as the test circuitry built especially for the develoment of this fuse-links are explained below.

• ETRI Journal
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• v.17 no.2
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• pp.21-30
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• 1995

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a one-time, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below $20{\Omega}$. The chip has been fabricated using a $0.8-{\mu}m$ n-well complementary metal oxide semiconductor technology with two layers of metalization.