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http://dx.doi.org/10.6109/jkiice.2013.17.10.2359

Design of Low-Noise and High-Reliability Differential Paired eFuse OTP Memory  

Kim, Min-Sung (Department of Electronic Engineering, Changwon University)
Jin, Liyan (Department of Electronic Engineering, Changwon University)
Hao, Wenchao (Department of Electronic Engineering, Changwon University)
Ha, Pan-Bong (Department of Electronic Engineering, Changwon University)
Kim, Young-Hee (Department of Electronic Engineering, Changwon University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.17, no.10, 2013 , pp. 2359-2368 More about this Journal
Abstract
In this paper, an IRD (internal read data) circuit preventing the reentry into the read mode while keeping the read-out DOUT datum at power-up even if noise such as glitches occurs at signal ports such as an input signal port RD (read) when a power IC is on, is proposed. Also, a pulsed WL (word line) driving method is used to prevent a DC current of several tens of micro amperes from flowing into the read transistor of a differential paired eFuse OTP cell. Thus, reliability is secured by preventing non-blown eFuse links from being blown by the EM (electro-migration). Furthermore, a compared output between a programmed datum and a read-out datum is outputted to the PFb (pass fail bar) pin while performing a sensing margin test with a variable pull-up load in consideration of resistance variation of a programmed eFuse in the program-verify-read mode. The layout size of the 8-bit eFuse OTP IP with a $0.18{\mu}m$ process is $189.625{\mu}m{\times}138.850{\mu}m(=0.0263mm^2)$.
Keywords
Power IC; Low-noise; High-reliability; Differential paired eFuse; Program-verify-read mode;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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