• 제목/요약/키워드: Fully-depleted

검색결과 52건 처리시간 0.028초

산소-아세틸렌 토치의 조사각이 ZrB2-SiC UHTC 복합체 삭마 특성에 미치는 영향 (Ablation Behavior of ZrB2-SiC UHTC Composite under Various Flame Angle Using Oxy-Acetylene Torch)

  • 이승용;공정훈;송정환;손영일;김도경
    • 한국재료학회지
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    • 제32권12호
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    • pp.553-559
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    • 2022
  • In this work, the ablation behavior of monolith ZrB2-30 vol%SiC (Z30S) composites were studied under various oxy-acetylene flame angles. Typical oxidized microstructures (SiO2/SiC-depleted/ZrB2-SiC) were observed when the flame to Z30S was arranged vertically. However, formation of the outmost glassy SiO2 layer was hindered when the Z30S was tilted. The SiC-depleted region was fully exposed to air with reduced thickness when highly tilted. Traces of the ablated and island type SiO2 were observed at intermediate flame angles, which clearly verified the effect of flame angle on the ablation of the SiO2 layer. Furthermore, the observed maximum surface temperature of the Z30S gradually increased up to 2,200 ℃ proving that surface amorphous silica was continuously removed while monoclinic ZrO2 phase began to be exposed. A proposed ablation mechanism with respect to flame angles is discussed. This observation is expected to contribute to the design of complex-shaped UHTC applications for hypersonic vehicles and re-entry projectiles.

후속열처리 공정을 이용한 FD Strained-SOI 1T-DRAM 소자의 동작특성 개선에 관한 연구

  • 김민수;오준석;정종완;조원주
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 추계학술대회 논문집
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    • pp.35-35
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    • 2009
  • Capacitorless one transistor dynamic random access memory (1T-DRAM) cells were fabricated on the fully depleted strained-silicon-on-insulator (FD sSOI) and the effects of silicon back interface state on buried oxide (BOX) layer on the memory properties were evaluated. As a result, the fabricated 1T-DRAM cells showed superior electrical characteristics and a large sensing current margin (${\Delta}I_s$) between "1" state and "0" state. The back interface of SOI based capacitorless 1T-DRAM memory cell plays an important role on the memory performance. As the back interface properties were degraded by increase rapid thermal annealing (RTA) process, the performance of 1T-DRAM was also degraded. On the other hand, the properties of back interface and the performance of 1T-DRAM were considerably improved by post RTA annealing process at $450^{\circ}C$ for 30 min in a 2% $H_2/N_2$ ambient.

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SOI Image Sensor Removed Sources of Dark Current with Pinned Photodiode on Handle Wafer (ICEIC'04)

  • Cho Y. S.;Lee C. W.;Choi S. Y.
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 학술대회지
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    • pp.482-485
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    • 2004
  • We fabricated a hybrid bulk/fully depleted silicon on insulator (FDSOI) complementary metal oxide semiconductor (CMOS) active pixel image sensor. The active pixel is comprised of reset and source follower transistors on the SOI seed wafer, while the pinned photodiode and readout gate and floating diffusion are fabricated on the SOI handle wafer after the removal of the buried oxide. The source of dark current is eliminated by hybrid bulk/FDSOI pixel structure between localized oxidation of silicon (LOCOS) and photodiode(PD). By using the low noise hybrid pixel structure, dark currents qm be suppressed significantly. The pinned photodiode can also be optimized for quantum efficiency and reduce the noise of dark current. The spectral response of the pinned photodiode on the SOI handle wafer is very flat between 400 nm and 700 nm and the dark current that is higher than desired is about 10 nA/cm2 at a $V_{DD}$ of 2 V.

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The Short Channel Effect Immunity of Silicon Nanowire SONOS Flash Memory Using TCAD Simulation

  • Yang, Seung-Dong;Oh, Jae-Sub;Yun, Ho-Jin;Jeong, Kwang-Seok;Kim, Yu-Mi;Lee, Sang Youl;Lee, Hi-Deok;Lee, Ga-Won
    • Transactions on Electrical and Electronic Materials
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    • 제14권3호
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    • pp.139-142
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    • 2013
  • Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

Short-gate SOI MESFET의 문턱 전압 표현 식 도출을 위한 해석적 모델 (An Analytical Model for Deriving The Threshold Voltage Expression of A Short-gate Length SOI MESFET)

  • 갈진하;서정하
    • 대한전자공학회논문지SD
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    • 제45권7호
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    • pp.9-16
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    • 2008
  • 본 논문에서는 short-gate SOI MESFET의 문턱전압 도출을 위한 간단한 해석적 모델을 제시하였다. 완전 공핍된 실리콘 채널 영역에서는 2차원 Poisson 방정식을, buried oxide 영역에서는 2차원 Laplace 방정식을 반복법(iteration method)을 이용해 풀어 각 영역 내에서의 전위 분포를 채널에 수직한 방향의 좌표에 대해 5차 다항식으로 표현하였으며 채널 바닥 전위를 구하였다. 채널 바닥 전위의 최소치가 0이 되는 게이트 전압을 문턱 전압으로 제안하여 closed-form의 문턱 전압 식을 도출하였다. 도출된 문턱 전압 표현 식을 모의 실험한 결과, 소자의 구조 parameter와 가해진 bias 전압에 대한 정확한 의존성을 확인할 수 있었다.

천연가스 고체화 수송을 위한 메탄 하이드레이트 충진율 증대에 대한 실험적 연구 (Experimental Investigation on the Enhancement of Methane Hydrate Formation in the Solid Transportation of Natural Gas)

  • 김남진;정재성;김종보
    • 설비공학논문집
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    • 제14권10호
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    • pp.863-870
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    • 2002
  • Fossil fuels have been depleted gradually and new energy resource which can solve this shortage is needed now. Methane hydrate, non-polluting new energy resource, satisfies this requirement and considered the precious resource prevent the global warming. Fortunately, there are abundant resources of methane hydrate distribute in the earth widely, so developing the techniques that can use these gases effectively is fully valuable. the work presented here is to develop the skill which can transport and store methane hydrate. As a first step, the equilibrium point experiment has been carried out by increasing temperatures in the cell at fixed pressures. The influence of gas consumption rates under variable degree of subcooling, stirring and water injection has been investigated formation to find out kinetic characteristics of the hydrate. The results of present investigation show that the enhancements of the hydrate formation in terms of the gas/water ratio are closely related to operational pressure, temperature, degrees of subcooling, stirring rate, and water injection.

Effect of Nutritional Requirements and Feeding Regimes at First Feeding on the Survival of the Larval Olive Flounder Paralichthys olivaceus

  • Cabrera Tomas;Hur Sung Bum
    • Fisheries and Aquatic Sciences
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    • 제8권4호
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    • pp.228-234
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    • 2005
  • Despite the relatively high production of fingerlings of the olive flounder Paralichthys olivaceus, its larval rearing in terms of first feeding has not been fully analyzed. We evaluated the variations of amino acids and fatty acids of starved larvae over 96 hr after hatching. We also investigated depletion of the yolk and oil globule of starved larvae and those fed the rotifer Brachionus plicatilis. In addition, the optimum size of the rotifers according to the mouth size of the larvae, and the point of no return with delay of the first feeding, were also examined. The amino acids in the egg decreased abruptly during embryo development. At 48 to 72 hr after hatching, the amino acids of starved larvae decreased by $30-40\%$ from the level in newly hatched larvae. The concentrations of fatty acids in newly hatched larvae were lower than those of floating eggs and dropped sharply at 48 hr after hatching, when the yolk disappeared. The starved larvae depleted their yolksacs and oil globules earlier than the fed larvae did. At 84 hr after hatching, rotifers were detected for the first time in the guts of the larvae, which were about 3 mm in total length. The point of no return appeared to be close to the fourth day from the first feeding. For a high survival rate of P. olivaceus larvae, the first feeding should occur before the third day after hatching.

The technological state of the art of wave energy converters

  • GURSEL, K. Turgut
    • Advances in Energy Research
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    • 제6권2호
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    • pp.103-129
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    • 2019
  • While global demand for energy increases annually, at the same time the demand for carbon-free, sulphur-free and NOx-free energy sources grows considerably. This state poses a challenge in the research for newer sources like biomass and shale gas as well as renewable energy resources such as solar, wind, geothermal and hydraulic energy. Although wave energy also is a form of renewable energy it has not fully been exploited technically and economically so far. This study tries to explain those reasons in which it is beyond doubt that the demand for wave energy will soon increase as fossil energy resources are depleted and environmental concerns gain more importance. The electrical energy supplied to the grid shall be produced from wave energy whose conversion devices can basically work according to three different systems. i. Systems that exploit the motions or shape deformations of their mechanisms involved, being driven by the energy of passing waves. ii. Systems that exploit the weight of the seawater stored in a reservoir or the changes of water pressure by the oscillations of wave height, iii. Systems that convert the wave motions into air flow. One of the aims of this study is to present the classification deficits of the wave energy converters (WECs) of the "wave developers" prepared by the European Marine Energy Center, which were to be reclassified. Furthermore, a new classification of all WECs listed by the European Marine Energy Center was arranged independently. The other aim of the study is to assess the technological state of the art of these WECs designed and/or produced, to obtain an overview on them.

SOI형 대칭 DG MOSFET의 문턱전압 도출에 대한 간편한 해석적 모델 (A simple analytical model for deriving the threshold voltage of a SOI type symmetric DG-MOSFET)

  • 이정호;서정하
    • 대한전자공학회논문지SD
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    • 제44권7호통권361호
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    • pp.16-23
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    • 2007
  • 본 논문에서는 완전 공핍된 SOI형 대칭 이중게이트 MOSFET의 문턱 전압에 대한 간단한 해석적 모델을 제시하고자 실리콘 몸체 내의 전위 분포를 근사적으로 채널에 수직한 방향의 좌표에 대해 4차 다항식으로 가정하였다. 이로써 2차원 포아송 방정식을 풀어 표면 전위의 표현식을 도출하고, 이 결과로부터 드레인 전압 변화에 의한 문턱 전압의 roll-off를 비교적 정확하게 기술할 수 있는 문턱 전압의 표현식을 closed-form의 간단한 표현식으로 도출하였다. 도출된 표현식으로 모의 실험을 수행한 결과 $0.01\;[{\mu}m]$의 실리콘 채널 길이 범위까지 채널 길이에 지수적으로 감소하는 것을 보이는 비교적 정확한 결과를 얻을 수 있음을 확인하였다.

Enhancement of On-Resistance Characteristics Using Charge Balance Analysis Modulation in a Trench Filling Super Junction MOSFET

  • Geum, Jongmin;Jung, Eun Sik;Kim, Yong Tae;Kang, Ey Goo;Sung, Man Young
    • Journal of Electrical Engineering and Technology
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    • 제9권3호
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    • pp.843-847
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    • 2014
  • In Super Junction (SJ) MOSFETs, charge balance is the most important issue of the SJ fabrication process. In order to achieve the best electrical characteristics, such as breakdown voltage and on-resistance, the N-type and P-type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, which is known as the charge balance condition. In conventional charge balance analysis, based on multi-epi process SJ MOSFETs, analytical model has only N, P pillar width and doping concentration parameter. But applying a conventional charge balance principle to trench filling process, easier than Multi-epi process, is impossible due to the missing of the trench angle parameter. To achieve much more superior characteristics of on-resistance in trench filling SJ MOFET, the appropriate trench angle is necessary. So in this paper, modulated charge balance analysis is proposed, in which a trench angle parameter is added. The proposed method is validated using the TCAD simulation tool.