• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.97-103
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• 2014

In this paper, a clock-data recovery using a 1/8-rate phase detector is proposed. The use of a conventional full or half-rate phase detector requires relatively higher frequency of a recovered clock, which is a burden on the design of a sampling circuit and a VCO. In this paper, a 1/8-rate phase detector is used to lower the frequency of the recovered clock and a linear equalizer is used as a input circuit of a phase detector to reduce the jitter of the recovered clock. A test chip fabricated in a 0.13-${\mu}m$ CMOS process is measured at 1.5-GHz for a 3-Gb/s PRBS input and 1.2-V power supply.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.67-88
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• 2005

Mold-Flow 3 Die Stack CSP of Mold array packaging with different Gate types. As high density package option such as 3 or 4 die stacking technologies are developed, the major concerning points of mold related qualities such as incomplete mold, exposed wires and wire sweeping issues are increased because of its narrow space between die top and mold surface and higher wiring density. Full 3D rheokinetic simulation of Mold flow for 3 die stacking structure case was done with the rheological parameters acquired from Slit-Die rheometer and DSC of commercial EMC. The center gate showed severe void but corner gate showed relatively better void performance. But in case of wire sweeping related, the center gate type showed less wire sweeping than corner gate types. From the simulation results, corner gate types showed increased velocity, shear stress and mold pressure near the gate and final filling zone. The experimental Case study and the Mold flow simulation showed good agreement on the mold void and wire sweeping related prediction. Full 3D simulation methodologies with proper rheokinetic material characterization by thermal and rheological instruments enable the prediction of micro-scale mold filling behavior in the multi die stacking and other complicated packaging structures for the future application.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.10
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• pp.541-547
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• 2001

Testing a core-based designed chip requires a full isolation ring to provide fro core test data access to each core. A partial isolation ring replaces the full isolation ring reducing total isolation ring size surrounding. This paper proposes an efficient method to reduce the size of the partial isolation ring and shorten the time to acquire the final solution. For this, a reasonable ordering technique according to testability is introduced and a sorting technique is adopted to reduce the total solution time. Experimental results show that the proposed method can be useful in practice.

• Journal of the Optical Society of Korea
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• v.11 no.1
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• pp.18-25
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• 2007

We present an ultrahigh-resolution full-field optical coherence tomography (FF-OCT) implemented with a white-light interference microscope and a detector array as an alternative OCT technique. The use of detector array allows the capture of two-dimensional en-face images in parallel without taking any lateral scanning process. The phase shifting interferometric technique with the sinusoidal phase modulation (SPM) is utilized to get the demodulated OCT images. The configuration of the system and the resolution of the obtained image are presented. The topographic images, taken with the implemented system, of a coin, an integrated circuit chip, and the tomographic images of an onion epithelium are demonstrated also. Axial and lateral spatial resolution of ${\sim}1.0{\mu}m$ and ${\sim}2.0{\mu}m$ are achieved with the system respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.571-574
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• 2008

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.3
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• pp.531-536
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• 2009

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure around the unit pixel. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.22-28
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• 2008

This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.9
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• pp.114-129
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• 1996

This paper describes the whole development phase for the underwater vehicle actuating system with high hydroload torque disturbance. This includes requirement analysis, system modeling, control algorithm design, real time implementation, test and performance evaluations. As for driving control algorithms, fuzzy logic, variable structure and PD(Proportional-Differential) algorithm were designed and implemented on board controller using a single chip microprocessor. Intel 8797. And test and performance evaluation is carried out both single test and wystem integration test. We could confirm the basic performance of actuating system through the single test and gereral developing work of any actuating systems was finished with a single performance test of actuating system without system integration test. But, we suggested that system integration test be needed. System integration test is carried out using G/C HILS(Guidance and Control Hardware-In-the -Loop Simulation) which is constituted flight motion simulator, load simulator, real time host computer and the related subsystems such as inertial navigation system, power supply system and Guidance and Control Computer etc.. The most important practical contribution of this paper is that full system characteristics such as minimal control effort, enhancement of guidance and autopilot performance by the actuating system using G/C HILS technique are investigated. Through full running G/C HILS, in spite of the passing to single tests, some control algorithm resulted in failure as to stability of full system and system time frame.

• ETRI Journal
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• v.36 no.5
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• pp.829-834
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• 2014

In this paper, a lateral power metal-oxide-semiconductor field-effect transistor with ultra-low specific on-resistance is proposed to be applied to a high-voltage (up to 200 V) integrated chip. The proposed structure has two characteristics. Firstly, a high level of drift doping concentration can be kept because a tilt-implanted p-drift layer assists in the full depletion of the n-drift region. Secondly, charge imbalance is avoided by an extended trench gate, which suppresses the trench corner effect occurring in the n-drift region and helps achieve a high breakdown voltage (BV). Compared to a conventional trench gate, the simulation result shows a 37.5% decrease in $R_{on.sp}$ and a 16% improvement in BV.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.241-250
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• 1996

In this work, an improved architecture of two-dimensional digital filter(2D DF) is suggested, and then the filter is simulated by C, VHDL language and related layouts are designed by Berkeley CAD tools. The 2D DF consists of one-dimensional digital filters and delay lines. For one-dimensional digital filter(1D DF) case, once filter coefficients are represented by canonical signed digit formats, multiplications are exected by hardwired-shifting methods. The related bit numbers are handled to prevent picture quality degradation and pipelined adder architectures are adopted in each tap and output stage to speed up the filter. For delay line case, line-sharing DRAM is adopted to improve power dissipation and speed. The filter layout is designed by semi/full custom methods considering regularity and speed improvement, and normal operation is confirmed by simulation.