• 제목/요약/키워드: Folding

검색결과 1,064건 처리시간 0.043초

2단 접이식 산업용 자동문의 동역학적 메카니즘 해석 (Dynamical Mechanism Analysis of An Industrial Two-step Folding Automatic Door)

  • 윤성호
    • 한국정밀공학회지
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    • 제28권7호
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    • pp.821-826
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    • 2011
  • This paper deals with an analysis of dynamic mechanism for the industrial two-step folding automatic door. A nonlinear equation of motion was derived in terms of folding angle to estimate driving forces. Based on this dynamic behavior, time taken during the door's opening well as their velocities were controlled so that the operating conditions can be obtained for the purpose of design. The stiffness of twisting spring was also investigated when the automatic door closed, because a dangerous accident takes place from the door's free falling. The current research will be a very useful tool in the near future for the dynamic analysis for the multi-step folding automatic door.

3.3V 8-bit 200MSPS CMOS folding/interpolation ADC의 설계 (Design of a 3.3V 8-bit 200MSPS CMOS folding/interpolation ADC)

  • 송민규
    • 대한전자공학회논문지SD
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    • 제38권3호
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    • pp.44-44
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    • 2001
  • 본 논문에서는 CMOS로 구현된 3.3V 8-bit 200MSPS의 Folding / Interpolation 구조의 A/D 변환기를 제안한다. 회로에 사용된 구조는 FR(Folding Rate)이 8, NFB(Number of Folding Block)가 4, Interpolation rate 이 8이며, 분산 Track and Hold 구조를 회로를 사용하여 Sampling시 입력주파수를 Hold하여 높은 SNDR을 얻을 수 있었다. 고속동작과 저 전력 기능을 위하여 향상된 래치와 디지털 Encoder를 제안하였고 지연시간 보정을 위한 회로도 제안하였다. 제안된 ADC는 0.35㎛, 2-Poly, 3-Metal, n-well CMOS 공정을 사용하여 제작되었으며, 유효 칩 면적은 1070㎛×650㎛ 이고, 3.3V전압에서 230mW의 전력소모를 나타내었다. 입력 주파수 10MHz, 샘플링 주파수 200MHz에서의 INL과 DNL은 ±1LSB 이내로 측정되었으며, SNDR은 43㏈로 측정되었다.

폴딩 블라인드 리벳의 제조기술에 관한 연구 (A Study on the Manufacturing Technology of a Folding Blind Rivet)

  • 변홍석;김영호
    • 한국생산제조학회지
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    • 제20권1호
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    • pp.67-73
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    • 2011
  • In this study, the manufacturing technology of a folding blind rivet was developed through finite element analysis(FEA). Numerical simulations of the folding blind rivet used to join two components have been performed with the finite element method for the forging process design. To minimize the process and manufacture the folding blind rivet without defects, a variety of design rules were proposed. From the results of FEA applied process design rules, an optimal six-stage process was proposed. The finite element simulation results such as shape of the forged rivet, strain distribution and forging load were investigated for the usefulness of the forging process of the blind rivet. In addition, the experiments have been implemented and their results were compared to the analytic results.

접히는 특성을 가진 스너버 망으로 소프트하게 복귀하는 의사 펄스 폭 변조 컨버터 (Soft recovery PWM Quasi-Resonance Converter With a Folding Snubber Network)

  • 정진국
    • 전자공학회논문지SC
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    • 제47권2호
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    • pp.50-54
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    • 2010
  • 반감(半減)되는 특성을 가진 폴딩 스너버 망을 내포하므로 소프트하게 역 복귀 되는 새로운 형태의 의사 공진 펄스 폭 변조 컨버터를 소개한다. 이 컨버터는 이미 소개된 기존의 QRC에 단지 수동소자만으로 구성된 폴딩 스너버를 결합하여 구현시켰다. 이용된 수동소자는 단지 다이오드와 케페시터로 구성되었다. 이렇게 제안된 펄스 폭 변조 컨버터의 효율은 매우 높아 대 전류를 출력시키는 DC-DC 컨버터의 응용에 매우 적합하다.

경첩구조를 이용한 접이식 가구에 관한 연구 (A Study on Folding Furniture through the Structure of Hinges)

  • 조남주
    • 한국가구학회지
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    • 제12권2호
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    • pp.81-90
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    • 2001
  • For opening and shutting function, door has some hardware such as hinges and the locks. The folding mechanism of hinges represent mobility, and the lock means stability. The opening and shutting door-the mobility-could be interpreted the movement from flat state to three-dimensional structure. The folding mechanism also would be understood variable feature to the space. This study focus on the Folding Furniture which adapted the good point of hinges to make efficient use of the space. The folding furniture presented in this study has not only artistic meaning which expand and apply structural function of hinges, but also flexible reanalysis on the environment and the space which change with social, economic and cultural trend.

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폴딩 도어 메커니즘 설계를 위한 기구학 및 동역학 해석 프로그램 개발 (Development of the Kinematic and Dynamic Analysis Program for the Design of the Folding Door Mechanism)

  • 서명원;권성진;심문보;조기용;이은표;박승영
    • 한국자동차공학회논문집
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    • 제10권6호
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    • pp.187-193
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    • 2002
  • Since the bus is regarded as the one of the most public transportation systems, research on the safety and facilities of the bus has been increased actively in recent years. In this paper, we concern the design of the bus door mechanism that is composed of many linkages and actuators(or motors). In particular, the folding door mechanism is representative system installed in most of urban buses. To design the folding door mechanism, we construct the kinematic and dynamic analysis model fur computer simulation. Also, the dynamic analysis is accomplished by both direct dynamics and inverse dynamics. Since the folding door mechanism has many design variables, the analysis program is developed to perceive kinematic and dynamic characteristics according to the design variables and simulation conditions.

폴딩을 이용한 구조와 형태 (Structure and Form Derived from Folding; from Pleated Shape to Deployable Structure)

  • 박선우;최선영;최취경
    • 한국공간구조학회논문집
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    • 제7권2호
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    • pp.45-52
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    • 2007
  • 폴딩은 면에 기하학적 형태를 부여하는 동시에 역학적 효율을 증대시킬 수 있다. 본 연구의 목적은 건축의 조형성에 영향을 미칠 수 있는 폴딩을 구조와 형태의 매개로서 탐구하고, 그 역할과 가능성을 고찰하는 것이다. 따라서 먼저 폴딩의 특성과 패턴형성의 요소 및 이를 이용한 공간의 구성양식을 살펴본다. 또한 절판구조와 막구조에서 보이는 폴딩의 변형과 응용 방법을 파악함으로써 조형요소로서 역할과 가능성을 확인하고, 전개성을 응용한 형태로서 전개구조의 가능성을 확인한다.

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A 3.3V 10BIT CURRENT-MODE FOLDING AND INTERPOLATING CMOS AJ D CONVERTER USING AN ARITHMETIC FUNCTIONALITY

  • Chung, Jin-Won;Park, Sung-Yong;Lee, Mi-Hee;Yoon, Kwang-Sub
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 ITC-CSCC -2
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    • pp.949-952
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    • 2000
  • A low power 10bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3V The proposed ADC is implemented by a 0.6${\mu}$m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of ${\pm}$0.5LSB, an integral nonlinearity (INL) of ${\pm}$1.0LSB

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Characterization of Protein Disulfide Isomerase during Lactoferrin Polypeptide Structural Maturation in the Endoplasmic Reticulum

  • Lee, Dong-Hee;Kang, Seung-Ha;Choi, Yun-Jaie
    • BMB Reports
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    • 제34권2호
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    • pp.102-108
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    • 2001
  • A time-dependent folding process was used to determine whether or not protein disulfide isomerase (PDI) plays an important role in the maturation of nascent lactoferrin polypeptides. Interaction between lactoferrin and PDI was analyzed according to the co-immunoprecipitation of the two proteins. The results indicate that lactoferrin folding requires a significant interaction with PDI and its binding is relatively brief compared to other nascent polypeptides. The amount of lactoferrin interacting with PDI increases up to half a minute and sharply decreases beyond this time point. During the refolding process that follows reduction by DTT, lactoferrin polypeptides heavily interact with PDI and the interaction period was extended compared to the normal folding process. In terms of the temperature effect on PDI-lactoferrin interaction, PDI binds to lactoferrin polypeptides longer at a lower temperature (here, $25^{\circ}C$) than $37^{\circ}C$. The lactoferrin-PDI interaction was also studied in vitro. According to the in vitro experiment data, PDI was still functional in cell lysates assisting lactoferrin folding into the mature form. PDI interacts with lactoferrin polypeptides for an extended period during the folding in vitro. During the refolding process in vitro, intermolecular aggregates and refolding oligomers matured into a functional form after PDI binds to the lactoferrin. These results suggest that PDI provides a prolonged chaperoning activity in the refolding processes and that there appears to be a greater requirement for PDI chaperone activity in the refolding of lactoferrin polypeptides.

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An 8-b 1GS/s Fractional Folding CMOS Analog-to-Digital Converter with an Arithmetic Digital Encoding Technique

  • Lee, Seongjoo;Lee, Jangwoo;Lee, Mun-Kyo;Nah, Sun-Phil;Song, Minkyu
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권5호
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    • pp.473-481
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    • 2013
  • A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.