• Journal of the Microelectronics and Packaging Society
• /
• v.10 no.2
• /
• pp.61-67
• /
• 2003

The interfacial reaction between ultra-small 58Bi-42Sn solder and Au/Ni/Ti under bump metallurgy (UBM) for ultra-fine flip chip application was investigated. The ultra-small 58Bi-42Sn solder bump, about $46{\mu}m$ in diameter, was fabricated by using the lift-off method and reflowed using the rapid thermal annealing (RTA) system. The intermetallic compounds were characterized using a secondary electron microscopy (SEM), an energy dispersive spectroscopy (EDS), and an x-ray diffractometer (XRD). The faceted and polygonal intermetallic compounds were found in the Bi-Sn solder bumps on $Au(0.1{\mu}m)/Ni/Ti$ UBM and they were indentified as $(Au_xBi_yNi_{1-x-y})Sn_2$ Phase. The intermetallic compounds grown from the $Au(0.1{\mu}m)/Ni/Ti$ UBMinterface were dispersed in the solder bump.

• Journal of the Microelectronics and Packaging Society
• /
• v.13 no.4
• /
• pp.37-43
• /
• 2006

Surface roughness and hardness of the electroplated Sn were characterized with variations of electroplating current density and current mode. The Sn electroplated at $5{\sim}50mA/cm^{2}$ exhibited the surface roughness of $2.0{\sim}2.4{\mu}m$. The Sn electroplated with pulse current mode exhibited low surface roughness compared one processed with direct current mode. With surface annealing at $300^{\circ}C$ for 3 sec using halogen lamp, surface roughness of the Sn bump was substantially reduced to $1{\mu}m$. The Sn electroplated at $5{\sim}50mA/cm^{2}$ exhibited the hardness of 10 Hv. Low contact resistances of $33{\sim}17m{\Omega}$ were obtained for specimens flip-chip bonded with Sn bumps.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.2
• /
• pp.35-39
• /
• 2012

We studied interfacial reaction and bonding characteristics of a flip chip bonding with the viewpoint of formation behavior of intermetallic compounds. For this purpose, Sn-0.7Cu and Sn-3Cu solders were reflowed on the Al/Cu and Al/Ni UBMs. When Sn-0.7Cu was reflowed on the Al/Cu UBM, no intermetallic compounds were formed at the solder/UBM interface. The $Cu_6Sn_5$ intermetallic compounds formed by reflowing Sn-3Cu solder on the Al/Cu UBM were spalled from the interface, resulting in delamination of the solder/UBM interface. On the other hand, the $(Cu,Ni)_6Sn_5$ intermetallic compounds were formed by reflowing of Sn-0.7Cu and Sn-3Cu on the Al/Ni UBM and the interfacial bonding between the Sn-Cu solders and the Al/Ni UBM was kept stable.

• Journal of Welding and Joining
• /
• v.29 no.6
• /
• pp.65-70
• /
• 2011

The effect of flip chip bonding parameters on formation of intermetallic compounds (IMCs) between Au stud bumps and Sn-3.5Ag solder was investigated. In this study, flip chip bonding temperature was performed at $260^{\circ}C$ and $300^{\circ}C$ with various bonding times of 5, 10, and 20 sec. AuSn, $AuSn_2$ and $AuSn_4$ IMCs were formed at the interface of joints and (Au, Cu)$_6Sn_5$ IMC was observed near Cu pad side in the joint. At bonding temperature of $260^{\circ}C$, $AuSn_4$ IMC was dominant in the joint compared to other Au-Sn IMCs as bonding time increased. At bonding temperature of $300^{\circ}C$, $AuSn_2$ IMC clusters, which were surrounded by $AuSn_4$ IMC, were observed in the solder joint due to fast diffusivity of Au to molten solder with increased bonding temperature. Bond strength of Au stud bump joined with Sn-3.5Ag solder was about 23 gf/bump and fracture mode of the joint was intergranular fracture between $AuSn_2$ and $AuSn_4$ IMCs regardless bonding conditions.

• Journal of the Microelectronics and Packaging Society
• /
• v.18 no.1
• /
• pp.41-47
• /
• 2011

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. Also, the need for high speed data transmission and reception coupled with the ever increasing demand for mobility in consumer devices has generated a great interest in low cost devices with smaller form-factors. The UWB BPF makes use of lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). In this paper, this filter shows 2.0 dB insertion loss and 15 dB return loss from 7.0 GHz to 9.0 GHz. To the best of our knowledge, the UWB band-pass-filter developed in this paper has the smallest size ($1.4\;mm{\times}1.2\;mm{\times}0.40\;mm$) while achieving equivalent electrical performance.

• Journal of Welding and Joining
• /
• v.26 no.1
• /
• pp.37-43
• /
• 2008

• Proceedings of the KWS Conference
• /
• 2000.04a
• /
• pp.170-173
• /
• 2000

• Journal of the Korean Society of Radiology
• /
• v.8 no.7
• /
• pp.371-376
• /
• 2014

The process of flip-chip bump bonding, Au wire bonding and encapsulation were sucessfully developed and modularized. The CdTe sensor and ROIC were optimally jointed together at $150^{\circ}C$ and $270^{\circ}C$ respectively under24.5 N for 30s. To make SnAg bump on ROIC easy to be bonded, the higher bonding temperature was established than CdTe sensor's. In addition, the bonding pressure was lowered minimally because CdTe Sensor is easier to break than Si Sensor. CdTe multi-energy sensor module observed were no electrical failures in the joints using developed flip chip bump bonding and Au wire bonding process. As a result of measurement, shearing force was $2.45kgf/mm^2$ and, it is enough bonding force against threshold force, $2kgf/mm^2s$.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.1
• /
• pp.1-6
• /
• 2014

Flip chip bonded LED packages possess lower thermal resistance than wire bonded LED packages because of short thermal path. In this study, thermal and bonding properties of flip chip bonded high brightness LED were evaluated for Au-Sn thermo-compression bonded LEDs and Sn-Ag-Cu reflow bonded LEDs. For the Au-Sn thermo-compression bonding, bonding pressure and bonding temperature were 50 N and 300oC, respectively. For the SAC solder reflow bonding, peak temperature was $255^{\circ}C$ for 30 sec. The shear strength of the Au-Sn thermo-compression joint was $3508.5gf/mm^2$ and that of the SAC reflow joint was 5798.5 gf/mm. After the shear test, the fracture occurred at the isolation layer in the LED chip for both Au-Sn and SAC joints. Thermal resistance of Au-Sn sample was lower than that of SAC bonded sample due to the void formation in the SAC solder.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.4
• /
• pp.69-74
• /
• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.