• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.4
• /
• pp.483-486
• /
• 2014

Although flip-chip interconnects have smaller parasitics than bonding wires, they should be carefully designed at 60 GHz. Insertion loss at a flip-chip transition may differ as much as 2 dB depending on design parameters. In this paper we present a comprehensive sensitivity analysis to optimize the flip-chip transition.

• Journal of the Microelectronics and Packaging Society
• /
• v.10 no.3
• /
• pp.9-17
• /
• 2003

In this paper, thermo-mechanical and rheological properties of NCPs (Non-Conductive Pastes) depending on silica filler contents and diluent contents were investigated. And then, thermal cycling (T/C) reliability of flip chip assembly using selected NCPs was verified. As the silica filler content increased, thermo-mechanical properties of NCPs were changed. The higher the silica filler content was added, glass transition temperature ($T_g$) and storage modulus at room temperature became higher. While, coefficient of thermal expansion (CTE) decreased. On the other hand, rheological properties of NCPs were significantly affected by diluent content. As the diluent content increased, viscosity of NCP decreased and thixotropic index increased. However, the addition of diluent deteriorated thermo-mechanical properties such as modulus, CTE, and $T_g$. Based on these results, three candidates of NCPs with various silica filler and diluent contents were selected as adhesives for reliability test of flip chip assemblies. T/C reliability test was performed by measuring changes of NCP bump connection resistance. Results showed that flip chip assembly using NCP with lower CTE and higher modulus exhibited better T/C reliability behavior because of reduced shear strain in NCP adhesive layer.

• Journal of the Microelectronics and Packaging Society
• /
• v.8 no.2
• /
• pp.37-42
• /
• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2001.04a
• /
• pp.27-34
• /
• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Transactions on Semiconductor Engineering
• /
• v.1 no.1
• /
• pp.14-22
• /
• 2023

This paper presents a low-power flip-flop(FF) circuit that minimizes the transition of internal nodes by using a dual change-sensing method. The proposed dual change-sensing FF(DCSFF) shows the lowest dynamic power consumption among conventional FFs, when there is no input data transition. From the measured results with 65nm CMOS process, the power consumption has been reduced by 98% and 32%, when the data activity is 0% and 100%, respectively, compared to conventional transmission gate FF(TGFF). Further, compared to change-sensing FF(CSFF), the power consumption of proposed DCSFF is smaller by 30%.

• Journal of the Microelectronics and Packaging Society
• /
• v.18 no.4
• /
• pp.19-25
• /
• 2011

The size reduction of the semiconductor chip and the improvement of the electrical performance have been enabled through the introduction of the Cu/Low-K process in modern electronic industries. However, Cu/Low-K has a disadvantage of the physical properties that is weaker than materials used for existing semiconductor manufacture process. It causes many problems in chip manufacturing and package processes. Especially, the delamination between the Cu layer and the low-K dielectric layer is a main defect after the temperature cycles. Since the Cu/Low-K layer is located on the top of the pad of the flip chip, the stress on the flip chip affects the Cu/Low-K layer directly. Therefore, it is needed to improve the underfill process or materials. Especially, it becomes very important to select the underfill to decrease the stress at the flip-chip and to protect the solder bump. We have solved the delamination problem in a 90 nm Cu/Low-K flip-chip package after the temperature cycle by selecting an appropriate underfill.

• Journal of the Korean Ceramic Society
• /
• v.50 no.3
• /
• pp.238-243
• /
• 2013

We investigated the effect of Pb-metal filler added to a hybrid paste(PbO-$Bi_2O_3-B_2O_3$-ZnO glass frit and Pb-powder), for joining flip-chip sat lower temperatures than normal. The glass transition temperature was detected at $250^{\circ}C$ and the softening point occurred at $330^{\circ}C$. As the temperature increased, the specific density decreased due to the volatility of the Pb-metal and boron component in the glass. When the glass was heat-treated at $350^{\circ}C$ for 5 min, XRD results revealed a crystalline $Pb_4Bi_3B_7O_{19}$ phase that had been initiated by the addition of Pb-filler in the hybrid paste. The addition of the Pb-metal filler caused are action between the Pb-metal and glass that accelerated the formation of the liquid phase. The liquid phase that formed, promoted bonding between the flip-chip substrate sat lower temperature.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2005.09a
• /
• pp.111-129
• /
• 2005

Pop provides OEMs and EMS with a platform to cost effectively expand options for logic + memory 3D integration - Expands device options by simplifying business logistics of stacking - Integration controlled at the system level to best match stacked combinations with system requirements - Eliminates margin stacking and expands technology reuse - Helps manage the huge cost impacts associated with increasing demand for multi media processing and memory. PoP is well timed to enable and leverage: - Mass customization of systems for different use (form, fit and function) requirements o Bband and apps processor + memory stack platforms - Logic transition to flip chip enables PoP size reduction o Area and height reduction. Industry standardization is progressing. Amkor provides full turn-key support for base package, memory package and full system integration.

• Journal of the Optical Society of Korea
• /
• v.18 no.6
• /
• pp.633-638
• /
• 2014

We report experimental behaviors of condensed $^{87}Rb$ atoms responding to changes in the trap potential of the atomchip. The two-types of adiabatic and non-adiabatic overall changes were implemented by changing the ramp-down speed of the chip-wire current, which can dominantly modify the one-axis magnetic field gradient. Under the adiabatic process, a pure condensate stayed in the initial spin state and collectively oscillated with both monopole and dipole modes, while an atomic cloud above the critical temperature exhibited sound waves in a dense ultracold gas. On the other hand, Bose-Einstein condensate atoms with non-adiabatic perturbation were split into spatially different positions by spin states through spin-flip. We investigated the split ratio among spin states depending on final evaporation frequency. Potential changes, of course, cause collective oscillations regardless of the changing process.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.45 no.10
• /
• pp.65-70
• /
• 2008

We design and fabricate the 94 GHz Coplanar waveguide(CPW)-to-rectangular waveguide transition that is transmits signal smoothly between the CPW, which is a popular transmission line of the planar circuits, and rectangular waveguide for the 94 GHz transceiver system. The proposed transition composed of the unilateral fin-line taper and open type CPW-to-slot-line transition is based on the hard and inflexible sapphire for the flip-chip bonding of the planar MMICs using conventional MMIC technology. We optimize a single section transition to achieve low loss by using an EM field solver of Ansoft's HFSS and fabricate the back- to-back transition that is measured by Anritsu ME7808A Vector Network Analyzer in a frequency range of $85{\sim}105$ GHz. From the measurement and do-embedding CPW with 3 mm length, an insertion and return loss of a single-section transition are 1.7 dB and more an 25 than at 94 GHz, respectively.